Development of low-voltage and low-power mixed-signal ICs using nano-scale multiple gate field-effect transistors

使用纳米级多栅极场效应晶体管开发低电压和低功耗混合信号IC

• 批准号: 342879-2012
• 负责人: ElSankary, Kamal
• 金额: $ 1.31万
• 依托单位: Dalhousie University
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2014
• 资助国家: 加拿大
• 起止时间: 2014-01-01 至 2015-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=549653
• 关键词: Development; low; voltage; power; mixed

The low-power and cost-effective Complementary Metal-Oxide-Semiconductor (CMOS) devices have forced the analog designers to develop integrated circuits (ICs) using digital CMOS technologies. Conventional nano-scale planar CMOS devices suffer from undesirable short-channel effects, such as high drain induced barrier lowering, substantial leakage currents due to threshold voltage roll-off, lower intrinsic gain, lower output impedance, lower dynamic range and poorer device matching. These non-idealities eventually degrade the performance of CMOS devices and pose a serious threat to ICs' performance.

低功耗、低成本的互补金属氧化物半导体（CMOS）器件迫使模拟设计人员使用数字CMOS技术开发集成电路（IC）。传统的纳米级平面CMOS器件遭受不期望的短沟道效应，例如高漏极感应势垒降低、由于阈值电压滚降而导致的大量泄漏电流、较低的固有增益、较低的输出阻抗、较低的动态范围和较差的器件匹配。这些非理想性最终会降低CMOS器件的性能，并对集成电路的性能构成严重威胁。