Fabrication and process modeling of silicon based material structures for nanoscale microelectronics and photonics

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This grant is to support an integrated research program in process modeling for silicon-based materials and processes with applications in nanoelectronics and integrated optoelectronics. Two lines of research will be developed over the next five years: 1. Defects and diffusion: We have published work on modeling Si-Ge interdiffusion (Hasanuzzaman and Haddara, 2008; Hasanuzzaman et al., 2009) and on modeling vacancy injection from the silicon-silicon nitride interface (Hasanuzzaman and Haddara, 2008). We have developed models for the growth of voids in bare silicon and in silicon substrates with strained SiGe thin films under different ambient conditions (in progress). We have coupled these data with measurement of diffusion behavior of dopants in identically processed samples to be able to obtain a complete picture of the defect behavior in Si and SiGe. Understanding the full picture of defect and diffusion behavior in Si and SiGe structures is critical for process modeling for microelectronic devices in the nanoscale, including scaled MOSFETs, high speed HBTs, and new device structures. 2. Nanowire fabrication and modeling: We have reported on our work with ternary nanowires (Fakhr et al., 2010) and have developed a comprehensive quantitative model that explains the dependence of wire morphology, radial and axial composition, and stacking fault density on process parameters such as growth rate, III/V flux ratio, and pressure (Fakhr et al., in process). We wish to extend both experiment and modeling to Si/SiGe/SiGeC nanowires. We will optimize the fabrication process for these wires, model their growth and composition, and study the electrical properties of undoped and doped wires.