RIA: Area-Efficient VLSI Implementation of Signal ProcessingAlgorithms via Multiple Coefficient Recoding

研究了实现单个数或多个乘数并行相乘的硬件多系数编码技术。考虑了记录的最佳技术和适当的VLSI架构实现。开发了在VLSI中生成多编码阵列的自动布局工具。研究了多系数重编码在FIR和IIR滤波、dft和矩阵计算等重要信号处理操作中的适用性。

Multiple coefficient recoding techniques for implementing the hardware to multiply a single number of many multiplicands in parallel are investigated. Optimal techniques for recording and appropriate VLSI architectural realizations are considered. Automated layout tools that produce multiple-recoded arrays in VLSI are developed. The applicability of multiple coefficient recoding to several important signal processing operations, including FIR and IIR filtering, DFTs and matrix computations are also studied.