RIA: Wafer Scale Integration of Fault Tolerant Multi- Processor Architectures

为了克服传统单处理器计算机系统的性能限制，多处理器体系结构正受到广泛的研究。超大规模集成电路（VLSI）和晶圆规模集成（WSI）将整个多处理器架构集成在一个晶圆上，通过消除长时间的片外信号延迟和互连，进一步提高了系统性能。然而，有效的容错方案是实现VLSI/WSI的必要条件，以达到实际的良率和可靠性水平。本研究正在开发实用的设计方法，能够在单个大面积VLSI电路上有效地实现规则互连结构的大型容错多处理器架构。本文基于非概率模型进行了研究，得出了可用于实际实施的实用结果。我们也在开发高效的晶圆测试和诊断方案。

Multiprocessor architectures are being widely investigated to overcome the performance limitations of traditional uniprocessor computer systems. VLSI and Wafer Scale Integration (WSI) of the entire multiprocessor architecture on a single wafer further enhance the system performance by eliminating long off-chip signal delay and interconnection. However, an efficient fault tolerance scheme is essential for the VLSI/WSI implementation to achieve a practical level of yield and reliability. This research is developing practical design methodologies capable of efficiently realizing large fault tolerant multiprocessor architectures of regular interconnection structure on a single large area VLSI circuit. The study is based on nonprobabilistic model to produce practical results which can be used in actual implementation. We are also developing efficient wafer testing and diagnosis schemes.