RIA: Test Generation for Synchronous Sequential Circuits

这项研究是关于同步时序电路的完全故障覆盖(以低成本)。正在研究一种测试生成策略，该策略缓解了现有测试生成过程的限制。这种方法的本质是多时间观测假设，它消除了通过观察电路在单个时间单元的响应来检测故障的要求。正在探索一种由单个和多个过渡性故障组成的故障模型，该模型涵盖了多个门级卡在故障上。测试生成程序针对中型和大型电路，被描述为子机的互连。这种电路的分解算法正在研究中。目前正在设计一套全面的工具，特别是为了实现完全的故障复盖。这些工具包括：测试生成、模拟、提取和分解程序。

This research is on complete fault coverage (at low cost) for synchronous sequential circuits. A test generation strategy, which alleviates the limitations of existing test generation procedures is being investigated. The essence of the approach is in the multiple time observation assumption, which removes the requirement that a fault be detected by observation of the circuit's response at a single time unit. A fault model comprised of single and multiple transition faults, which covers many gate level stuck at faults, is being explored. Test generation procedures are aimed at medium sized and large circuits, described as interconnections of submachines. Algorithms for decomposition of such circuits are being investigated. A comprehensive set of tools is being designed especially for the purpose of achieving complete fault coverage. The tools include: test generation, simulation, extraction and decomposition procedures.