NYI: Performance Optimization in Layout and Logic Synthesis of VLSI Systems

本研究探讨了性能驱动的方法和有效算法， 高速、高复杂度VLSI系统的布局设计和逻辑综合。 的 性能驱动版图的研究主要集中在互连设计过程，包括 开发精确的互连模型，从而实现有效的布局 优化算法，用于电路划分和聚类的有效算法， 互连驱动布图规划和布局，具有缓冲器的互连拓扑设计 插入、同时的器件和互连尺寸以及时钟布局优化。 的 性能驱动逻辑综合的研究主要集中在综合和映射方面 用于现场可编程门阵列（FPGA），包括最佳或接近最佳 结构和功能门分解算法，最小延迟技术 技术映射中的延迟和面积的映射折衷，组合重定时， 技术映射和时钟周期最小化的重新合成，以及自动 流水线

This research investigated methodologies and efficient algorithms for performance-driven layout design and logic synthesis of high-speed, high-complexity VLSI systems. The research on performance-driven layout focuses on interconnect design process, including the development of accurate interconnect models which enable efficient layout optimization algorithms, efficient algorithms for circuit partitioning and clustering , interconnect-driven floorplan and placement, interconnect topology design with buffer insertin, simultaneous device and interconnect sizing, and clock layout optimization. The research on performance-driven logic synthesis mainly focus on synthesis and mapping for field-programmable gate-arrays (FPGAs), including optimal or near-optimal algorithms for structural and functional gate decomposition, minimum-delay technology mapping trade-off of delay and area in technology mapping, combined retiming, technology mapping, and resynthesis for clock period minimization, and automatic pipelining.