Operational Center for Silicon Wafer Engineering and Defect Science (Si WEDS)

摘要EEC-9726176 Rozgoni 为了在集成电路工业中具有竞争力，硅芯片制造商必须不断努力减小集成电路的部件的特征尺寸。 更小的特征尺寸使芯片制造商能够制造更小的芯片，满足市场对更小电子产品的需求，并提高每个硅晶片的芯片产量，降低每个芯片的成本。 为了确保高产量的高质量芯片，基础材料，硅晶片，必须尽可能没有体和表面缺陷和瑕疵。 据估计，为了满足2007年的生产需求，硅片中的缺陷密度必须低于0.01/cm 2。 目前还不知道如何以该行业能够承受的成本实现这一目标。 硅晶片工程和缺陷科学（Si Weds）的工业/大学合作研究中心计划提供关键解决方案，以提高硅材料的产量，性能和可靠性。 该中心位于北卡罗来纳州州立大学，是亚利桑那州立大学、亚利桑那大学、加州大学伯克利分校、麻省理工学院、南佛罗里达大学和斯坦福大学之间的合作伙伴。

ABSTRACT EEC-9726176 Rozgoni In order to be competitive in the integrated circuit industry, silicon chip manufacturers must continually strive to decrease the feature size of the components of the integrated circuits. A smaller feature size enables the chip manufacturers to both make smaller chips, fulfilling the market demand for ever smaller electronics, and to increase the yield of chips per silicon wafer, decreasing the cost per chip. In order to ensure high quality chips in high yields, the base material, the silicon wafer, must be as free from bulk and surface defects and imperfections as possible. It is estimated that in order to meet production demands in the year 2007, defect densities in silicon wafers must be below 0.01 per cm2. It is currently not known how this goal will be reached at a cost the industry can afford. The Industry/University Cooperative Research Center for Silicon Wafer Engineering and Defect Science (Si Weds) plans to provide critical solutions to increase yield, performance and reliability of silicon materials. The center is based at North Carolina State University, and is a partnership between Arizona State University, the University of Arizona, UC Berkeley, MIT, the University of South Florida, and Stanford University.