CAREER: Design Tools and Techniques for Analog Effects in Digital Integrated Circuits

这项研究解决了需要考虑数字电路和互连的模拟行为的细节，以确保正确的功能。重点分析了深亚微米电路设计中的时序和噪声问题。考虑了数字集成电路中的所有噪声源——信号线上的耦合噪声和振铃噪声、电源噪声和电路噪声。在性能验证中考虑了噪声对延迟的影响。由于许多新出现的时序和噪声问题都与片上电感有关，因此实际提取片上电感的技术将得到发展。如何将电感互连产生的复杂时域响应应用于静态时序和噪声分析，是目前研究的热点问题。另外的探索是利用由电感互连产生的复杂时域响应进行静态时序和噪声分析。其他研究领域包括芯片上电网完整性分析的静态解决方案以及合成和电路调谐中的噪声考虑。教育计划包括建立VLSI CAD研究实验室，以及开发使用fpga的硬件设计课程。

This research addresses the need to consider details of the analog behavior of digital circuits and interconnect in order to ensure correct functionality. Specifically it focuses on analysis of timing and noise in deep submicron circuit designs. All noise sources in a digital integrated circuit are being considered - coupled and ringing noise on signal lines, power supply noise, and noise from the circuits The effect of noise on delay is being considered in performance verification. Because many of the emerging timing and noise problems are associated with on-chip inductance, techniques for practically extracting on-chip inductance will be developed. The question of how the complex time-domain responses that result from inductive interconnect can be used in static timing and noise analysis is being investigated. Additional explorations are on using the complex time-domain responses that result from inductive interconnect for static timing and noise analysis. Other areas of investigation include a static solution to on-chip power grid integrity analysis and noise considerations in synthesis and circuit tuning. The educational plan includes building a VLSI CAD research laboratory, and development of courses in hardware design using FPGAs.