Patterned Heteroepitaxial Processing: A New Approach to Mismatched Heteroepitaxy for the Fabrication of High-Performance Semiconductor Devices
Patterned Heteroepitaxial Processing: A New Approach to Mismatched Heteroepitaxy for the Fabrication of High-Performance Semiconductor Devices
批准号:
9905874
负责人:
John Ayers
金额:
$3.53万
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
1999
资助国家:
美国
项目状态:
已结题
起止时间:
1999-07-01 至 2000-12-31
中文摘要
半导体的非匹配异质外延对于许多新型器件和集成电路的制造具有相当大的兴趣。这是因为相对较少的半导体衬底具有高晶体完美性和合适的电子性能。另一方面,许多与普通衬底晶圆(Si, GaAs和InP)不匹配的半导体在高速数字电子,微波集成电路,光电子学,光电子集成电路和太阳能电池方面具有重要的潜在应用。不幸的是,由于高密度的晶体缺陷,如螺纹位错(TD’s)和堆叠错误(SF’s),在器件和电路中使用高度不匹配的异质外延半导体非常有限。这些缺陷降低了多数载流子和少数载流子器件的性能,导致场效应晶体管的高泄漏电流和亚阈值退化,双极晶体管的电流增益差,发光二极管的效率和亮度差,以及注入激光器的快速退化和失效。目前,柔性衬底在降低错配异质外延半导体的缺陷密度方面显示出很大的前景。然而,在大面积衬底上的半导体高度不匹配的情况下,柔性衬底方法可能难以实现。这是因为这样的应用只需要几埃厚的柔性层,这是目前在大型晶圆上难以用现有技术生产的。PI提出了一种新的方法来实现没有螺纹位错的高度不匹配的异质外延半导体,这是对柔性衬底方法的补充。PI将他们的方法称为“图像化异质外延处理(PHP)”。PHP方法包括图像化的异质外延,或者连续层的图像化,然后是生长后退火。只要图案区域的横向尺寸足够小,PBP的任何一种变化都应该允许实现材料绝对没有螺纹位错。到目前为止,我们已经为PHP方法开发了一个定量模型,但是很少进行实验。在这里,他们建议对PHP进行实验评估。虽然该技术普遍适用于锌闪锌矿半导体,但他们将重点研究沉积在GaAs衬底上的ZnSSe材料。如果这一阶段是成功的,那么进一步的实验验证将是必要的,特别是与其他异质外延材料系统。建议的工作范围如下。他们将使用金属有机气相外延(MOVPE)在GaAs(001)衬底上沉积连续的ZnSSe层。不同的成分将允许他们将晶格错配从+0.27%调整到-4%。它们将在生长后将ZnSSe层图案化,形成不同尺寸的正方形和矩形区域。在生长后退火后,图案区域将使用湿化学蚀刻和扫描电子显微镜进行表征,以评估其螺纹位错密度。他们将使用他们现有的定量模型来指导我们设计实验。实验结果将用于为下一阶段的研究提出建议
英文摘要
9905874AyersMismatched heteroepitaxy of semiconductors is of considerable interest for the fabrication of many novel devices and integrated circuits. This is because relatively few semiconductor substrates are available with high crystal perfection and suitable electronic properties. On the other hand, many semiconductors not lattice-matched to the common substrate wafers (Si, GaAs, and InP) have important potential applications for high-speed digital electronics, microwave integrated circuits, optoelectronics, optoelectronic integrated circuits, and solar cells. Unfortunately, the use of highly-mismatched heteroepitaxial semiconductors in devices and circuits has been quite limited due to the high densities of crystal defects such as threading dislocations (TD's) and stacking faults (SF's). These defects degrade the performance of both majority- and minority-carrier devices, resulting in high leakage currents and subthreshold degradation in field-effect transistors, poor current gain for bipolar transistors, poor efficiency and brightness in light emitting diodes, and rapid degradation and failure in injection lasers.At the present time, compliant substrates show great promise for reducing the defect densities in mismatched heteroepitaxial semiconductors. However, the compliant substrate method may be difficult to implement in the case of highly-mismatched semiconductors on large area substrates. This is because such applications require compliant layers only a few angstroms thick, which are difficult to produce by presently available techniques on large wafers. The PI's have proposed a new approach to the achievement of highly mismatched heteroepitaxial semiconductors free from threading dislocations, which is complementary to the compliant substrate approach. The PI's call their approach "patterned heteroepitaxial processing (PHP)."The PHP approach involves either patterned heteroepitaxy, or the patterning of continuous layers followed by post-growth annealing. Either variation of PBP should allow the achievement of material absolutely free from threading dislocations as long as the lateral size of the patterned regions is small enough. To date we have developed a quantitative model for the PHP method, but very few experiments have been done. Here they propose to perform an experimental evaluation of PHP. Although the technique applies quite generally to zinc blende semiconductors, they will focus on ZnSSe material deposited on GaAs substrates for this work. If this phase is successful, then further experimental verification will be warranted, especially with other heteroepitaxial material systems.The scope of the proposed work is the following. They will deposit continuous layers of ZnSSe on GaAs (001) substrates using metalorganic vapor phase epitaxy (MOVPE). Different compositions will allow them to tailor the lattice mismatch from +0.27% to -4%. They will pattern the ZnSSe layers after growth, to square and rectangular areas of different dimensions. After post-growth annealing the patterned areas will be characterized using wet chemical etching and scanning electron microscopy to evaluate their threading dislocation densities. They will use their existing quantitative model as a guide in designing our experiments. The results of the experiments will be used to develop their recommendations for the next phase of research.***
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