Collaborative Research: High Quality Tests for Scan Circuits

本研究的目标是开发可扩展的程序，用于推导专门为包含扫描的数字逻辑电路设计的高质量测试，以增强可测试性。由于扫描（全扫描或部分扫描）目前在大多数电子芯片中使用，并且预计将继续成为设计范例（如基于核心的设计）中流行的可测试性设计技术，因此需要这样的程序。研究人员开发了测试生成、测试压缩、不可检测故障识别、内置测试生成和专门针对扫描电路的延迟故障测试的程序。在本研究中使用的测试应用方案中，在每两次扫描操作之间应用一个或多个主输入向量序列。在所有开发的程序中，目标是使用尽可能长的主输入向量序列。原因是主输入向量的长序列有助于电路的高速测试，这对于检测延迟缺陷很重要，并且它们允许测试数量保持低，从而减少测试应用时间。此外，电路在其正常运行模式下运行，可能导致正常运行时典型的平均功耗。几个商业工具使用了本研究中采用的测试应用方案，证明了其考虑的合理性。然而，文献中只有少数研究报告有效地解决了该方案下的各种测试问题。本研究开发的工具可以一起使用，为在该测试应用方案下与扫描电路测试相关的特殊问题提供全面和可扩展的解决方案。

The goal of this research is to develop scalable procedures for the derivation of high-quality tests specifically designed for digital logic circuits that contain scan to enhance testability. Such procedures are needed since scan (either full or partial scan) is currently used in most electronic chips, and is expected to continue to be the prevalent design-for-testability technique for design paradigms such as core-based design. The investigators develop procedures for test generation, test compaction, identification of undetectable faults, built-in test generation and delay fault testing specifically targeting scan circuits.In the test application scheme used in this research, a sequence of one or more primary input vectors is applied between every two scan operations. In all the procedures developed, the goal is to use sequences of primary input vectors that are as long as possible. The reasons are that long sequences of primary input vectors contribute to at-speed testing of the circuit, which is important for detecting delay defects, and they allow the number of tests to be kept low, which reduces the test application time. In addition, the circuit operates in its normal mode of operation, potentially resulting in average power consumption which is typical of normal operation. Several commercial tools use the test application scheme adopted in this research, justifying its consideration. However, only a small number of studies have been reported in the literature of effective solutions to the various testing problems under this scheme. This research develops tools that may be used together to provide a comprehensive and scalable solution to the special problems associated with testingof scan circuits under this test application scheme.