High-Performance Internet Router Architectures

随着通信链路速度超过每秒太比特，路由处理器上的分组处理正在成为网络服务的主要瓶颈。这两年的项目开发了必要的基准测试和仿真环境，以分析指令级并行、分支预测、推测执行、免锁定缓存和多处理等新体系结构思想对Internet路由器体系结构性能的影响。首先，它通过开发一组通常在高性能路由器上执行的通信基准程序来创建适当的工作负载。这些程序在商用处理器上执行，并与其他标准基准应用程序进行性能比较。该项目的主要贡献在于为路由器开发了一个执行驱动的模拟器，这些通信程序在这里编译和执行。该模拟器包含网络处理器、线路卡和主干交叉开关。模拟器的输入数据来自真实的互联网踪迹，如NLANR和UCB。通过将指令集设计、存储子系统、分组调度和多处理方面的新思想融入到模拟器中，本项目开发并测试了下一代互联网路由器的体系结构。

With communication link speed exceeding terabit per second, packet processing at the routing processors is becoming the main bottleneck in network services. The workload for these processors is very different compared to the general-purpose processors.The two-year project develops necessary benchmark and simulation environment to analyze the impact of new architectural ideas, such as instruction-level parallelism, branch prediction, speculative execution, lock-up free caches and multiprocessing, on the performance of Internet router architectures. First, it creates suitable workload by developing a set of communication benchmark programs that normally execute on high-performance routers. These programs are executed on commercially available processors and their performance is compared with other standard benchmark applications.The main contribution of the project lies in development of an execution-driven simulator for the router, where these communication programs are compiled and executed. The simulator incorporates the network processor, line cards, and the backbone crossbar switch. The input data to the simulator is obtained from real Internet traces, such as NLANR and UCB. By incorporating new ideas in instruction-set design, memory subsystem, packet scheduling, and multiprocessing into the simulator, architectures for the next-generation Internet routers are developed and tested in this project.