CAREER: Interconnect Design for Programmable Computation

互连一直是现场可编程门阵列及相关空间计算设备中消耗面积、时延和能耗最大的器件。由于互连要求的扩展速度快于器件门容量的线性扩展，而VLSI的基本互连延迟扩展速度慢于门速度，因此随着我们的发展，这个问题只会加剧。此外，随着我们今天可以构建的硅系统的规模，各种单芯片架构（例如多处理器、片上系统、VLIW、Vector、PIM）将朝着更大的片上并行性发展，从而更多地使用片上可编程互连。尽管如此，互连可能是可编程设备中最不容易理解的组件。本研究的基本目标是缩小我们对互连结构和互连需求量化的理解差距，并将这种理解综合到可编程互连设计的工程级方法中。这项工作将建立在VLSI和并行理论的基础上，但超越它们来缩小渐近差距，了解如何优化常数因素，并表征典型设计的特性和行为。教学目标是使具有计算机科学本科背景的学生和实践者能够理解空间互连设计的设计空间、问题、权衡和影响。

Interconnect has always been the dominant component consuming area, delay, and energy in Field-Programmable Gate Arrays and related spatial computing devices. With interconnect requirements scaling faster than linearly in device gate capacity and fundamental interconnect delays in VLSI scaling slower than gate speeds, this problem is only exacerbated as we go forward. Further, with the size of silicon systems we can build today, all kinds of single-chip architectures (e.g. multiprocessor, system-on-a-chip, VLIW, Vector, PIM) will be moving toward greater on-chip parallelism and hence greater use of on-chip, programmable interconnect.Nonetheless, interconnect is probably the least understood component in programmable devices. The fundamental goal of this research is to close gaps in our understanding of interconnect structures and in our quantification of interconnect requirements and synthesize this understanding into an engineering-grade approach to programmable interconnect design. This effort will build upon results in VLSI and Parallel theory, but goes beyond them to close asymptotic gaps, understand how to optimize the constant factors, and characterize the properties and behavior of typical designs. The pedagogical goal is to make the design space, issues, tradeoffs, and impact of spatial interconnect design accessible to students and practitioners with an undergraduate computer science background.