Design and Synthesis of Power Efficient Programmable Fabric

集成电路（IC）的制造成本的快速增加以及设计生产率和制造能力之间的差距的扩大可能会阻止IC技术根据摩尔定律继续发展。可编程器件提供了一种有吸引力的解决方案，通过重复使用相同的硅实现来显著降低每单位的摊销制造成本并显著提高设计生产率。 然而，现有的可编程电路和架构不是功率高效的。 在某些情况下，与定制IC设计相比，它们的功耗可能高出100倍。 该项目专注于研究和开发节能可编程电路结构和架构以及相关的综合工具，旨在将功耗降低10倍以上。我们的研究将遵循两个关键原则：（i）使用高度定量的方法进行电路和架构设计和优化;（ii）整合不同级别的优化技术，从电路级到结构级和系统级，最后是综合工具，用于开发具有最高功率效率的新型可编程器件。 本研究的成果包括：（1）一个灵活的功率评估框架，以实现可编程逻辑器件的精确定量评估;（2）新颖的电路和结构，以减少可编程器件中的泄漏和动态功耗;（3）新颖的实现时钟门控和功率门控的动态功率管理;以及（4）有效且高效的算法和工具，以支持上述电路级，结构级，和系统级优化技术。该项目的更广泛影响包括：（1）及时传播研究成果和进行技术转让，使可编程器件能够得到新的应用，从而使整个信息技术行业受益匪浅;（2）让研究生和可能的本科生参与拟议的研究，并将最新的研究方法/成果纳入教学中，这将有助于培养未来的研究人员和工程师，以进一步推动信息技术的发展。

Rapid increase of manufacturing costs of the integrated circuit (IC) and the widening gap between the design productivity and manufacturing capacity may prevent the IC technology from continuing to advance according to the Moore's Law. Programmable devices offer an attractive solution for significantly lowering the amortized manufacturing cost per unit and dramatically improving the design productivity through re-use of the same silicon implementation for a wide range of applications. However, existing programmable circuits and architectures are not power efficient. In some cases, they may consume 100x higher power compared to customized IC designs. This project focuses on research and development of power-efficient programmable circuit fabrics and architectures and associated synthesis tools, and is aimed to reduce the power dissipation by over 10x. Our research will be guided by two key principles: (i) the use of a highly quantitative approach to circuit and architecture design and optimization; (ii) the integration of different levels of optimization techniques, from circuit-level to fabric-level and system-level, and finally synthesis tools, for developing novel programmable devices with the highest power efficiency. Outcome of this research includes: (1) A flexible power evaluation framework to enable accurate quantitative evaluation of programmable logic devices; (2) Novel circuits and fabrics to reduce leakage and dynamic power in programmable devices; (3) Novel implementation of clock gating and power gating for dynamic power management; and (4) effective and efficient algorithms and tools to support the aforementioned circuit-level, fabric-level, and system-level optimization techniques.Broader impacts of this project include (1) Timely dissemination of research results and technology transfer to enable new applications of programmable devices that can significantly benefit the overall information technology (IT) industry; (2) Involvement of graduate and possibly undergraduate students in the proposed research and include the latest research methodologies/results into teaching, which will help to train future researchers and engineers for further advancement of the information technology.