Modeling, Design, and CMOS Performance Projections of Nanoscale Double-Gate FinFETs
Modeling, Design, and CMOS Performance Projections of Nanoscale Double-Gate FinFETs
批准号:
0424198
负责人:
Jerry Fossum
金额:
$0.0万
依托单位:
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2004
资助国家:
美国
项目状态:
已结题
起止时间:
2004-09-01 至 2007-08-31
中文摘要
本研究的目的是帮助和加快开发最佳设计的纳米级双栅(DG)FinFET的集成电路(IC)的应用超出了门长缩放限制(Lg ~ 45 nm)的传统或经典CMOS技术。虽然FinFET技术与传统MOSFET技术有关,非经典DG器件是准平面的,沟道和源极/漏极延伸形成在超薄垂直硅(Si)鳍片中。因此,由于掺杂剂杂质如何在这样薄的鳍中扩散的不确定性,器件处理是复杂的,并且由于这样薄的鳍中的静电和载流子传输的复杂物理,器件设计是复杂的。该研究将解决器件工艺和器件设计中的这些复杂问题,以及纳米级FinFET CMOS的项目性能。它将在很大程度上基于通用DG MOSFET的基于物理的紧凑模型(UFDG),具有少量直接与器件结构以及底层物理相关的基于工艺的参数。UFDG的工艺/物理基础使其具有准预测性,并且当在电路模拟器中实现时,能够预测非经典CMOS性能及其对制造工艺中预期波动的敏感性。该研究将包括三个阶段,所有这些都可能需要UFDG升级。首先,UFDG,辅以一套数字器件模拟器,将用于在飞思卡尔半导体(原摩托罗拉的一部分)制造的FinFET的逆建模,以学习如何有效地掺杂Si鳍,例如,源极/漏极扩展,以及如何表征鳍片中的掺杂分布。其次,UFDG和补充工具将用于优化设计FinFET,例如,关于栅极源极/漏极欠重叠(和偏压相关的Leff Lgate)及其对短沟道效应和Ion/Ioff比的控制。第三,UFDG/Spice 3将被用于设计具有最佳FinFET设计的CMOS性能。飞思卡尔的技术支持将帮助、验证和演示最佳设计。该研究的智力价值体现在两个主要贡献上:(1)关于纳米级FinFET的最佳设计和制造的物理见解和指导,包括实验演示,以及(2)可用于包括纳米级FinFET的CMOS电路的未来设计的可靠的基于物理的紧凑模型,in addition添加to aidingthe device设备technology技术development发展.该研究的更广泛影响将是对非经典纳米器件技术和物理领域的学生和工程师的教育,重点是FinFET,但具有广泛的应用基础,可以扩展到其他潜在可行的IC技术,超越传统CMOS的限制。在此基础上,确定新的研究生课程。而且,通过推动纳米IC技术的不断进步,半导体行业及其客户将受到积极的影响。
英文摘要
The objective of this research is to aid and expedite the development of optimally designednanoscale double-gate (DG) FinFETs for integrated circuit (IC) applications beyond the gatelengthscaling limit (Lg ~45nm) of today's conventional, or classical CMOS technologies.Although FinFET technology is related to conventional MOSFET technology, the nonclassicalDG device is quasi-planar with the channel and source/drain extensions formed in an ultra-thinvertical silicon (Si) fin. Thus, the device processing is complicated because of uncertainties inhow dopant impurities diffuse in such thin fins, and the device design is complicated because ofcomplex physics underlying the electrostatics and carrier transport in such thin fins. The researchwill address these complications in both device processing and device design, as well as projectperformances of nanoscale-FinFET CMOS. It will be based in large part on a physics-basedcompact model (UFDG) for generic DG MOSFETs, having a small number of process-basedparameters that relate directly to the device structure as well as the underlying physics. Theprocess/physics basis of UFDG renders it quasi-predictive and, when implemented in a circuitsimulator, capable of projecting nonclassical CMOS performance and its sensitivity to expectedfluctuations in the fabrication process. The research will comprise three stages, all of which couldnecessitate UFDG upgrades. First, UFDG, supplemented by a suite of numerical devicesimulators, will be used for inverse modeling of FinFETs fabricated at Freescale Semiconductor(formerly part of Motorola) to learn how to effectively dope the Si fins, e.g., the source/drainextensions, and how to characterize doping profiles in the fins. Second, UFDG and thesupplemental tools will be used to optimally design FinFETs, e.g., with regard to gatesource/drain underlap (and bias-dependent Leff Lgate) and its control of short-channel effectsand the Ion/Ioff ratio. Third, UFDG/Spice3 will be used to project CMOS performances withoptimal FinFET designs. Technological support from Freescale will aid, verify, and demonstratethe optimal designs.The intellectual merit of the research is reflected by its two main contributions: (1) physicalinsights and guidance regarding the optimal design and fabrication of nanoscale FinFETs,including experimental demonstration, and (2) a reliable physics-based compact model that couldbe used for future design of CMOS circuits comprising nanoscale FinFETs, in addition to aidingthe device technology development. The broader impacts of the research will be on theeducation of students and engineers in the area of nonclassical nanoscale device technologies andphysics, with emphasis on FinFETs but with a broad basis for application to other, potentiallyviable IC technologies that can be scaled beyond the limit of conventional CMOS. New graduatecourses will be defined based on the research. And, by promoting the continual advancement ofnanoscale IC technologies, the semiconductor industry and its customers will be impactedpositively.
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项目类别:Standard Grant
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资助金额:$21.37万
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