Checkpointed Processor Architectures

该项目提出了检查点处理器架构（checkpoint Processor Architectures， CPA），这是一种基于传统的按顺序提交支持和选择性状态检查点相结合的混合执行模式。CPA将资源回收与指令提交分离，允许更积极的回收和更高的利用率。它还执行一些长延迟内存操作的推测提交，允许后续指令完成并提交。为了从激进投机导致的损坏状态中恢复，CPA处理器依赖于它们的检查点状态。该项目将探索在处理器中集成CPA，支持同步多线程，以及芯片多处理器。该项目还将研究CPA和线程级推测之间的协同作用，这是一种即将到来的技术，可以弥合顺序计算和并行计算之间的差距。CPA脱离了传统的指令处理，将允许处理器提供更高的性能增长，而不会使关键资源过大，这对时钟速率有不利影响。因此，CPA将有助于克服进化处理器体系结构中的性能停滞。此外，我们对新兴并行和推测性并行架构的综合方法将确保产生广泛而持久的影响。最后，在CPA机制和交互中发展的见解将有助于更好地理解微处理器和并行体系结构在实验室和课堂上的协同设计方面。

Checkpointed Processor ArchitecturesAbstractThe project proposes Checkpointed Processor Architectures (CPA), a hybrid mode of execution based on a combination of traditional in-order commit support and selective state checkpointing. CPA decouples resource recycling from instruction commit permitting more aggressive reclamation and higher utilization. It also performs speculative commit of some long-latency memory operations, allowing subsequent instructions to complete and commit. To recover from corrupted states due to aggressive speculation, CPA processors rely on their checkpointed state. The project will explore the integration of CPA in processors with support for simultaneous multithreading, and with chip multiprocessors. The project will also investigate the synergy between CPA and thread-level speculation, an upcoming technology that bridges the gap between sequential and parallel computing.CPA's departure from traditional instruction processing will allow processors to deliver higher performance growth without oversizing critical resources, which affects the clock rate adversely. As a result, CPA will help overcome the performance stagnation in evolutionary processor architectures. Furthermore, our integrative approach with emerging parallel and speculatively parallel architectures will ensure a broad and lasting impact. Finally, the insights developed in the CPA mechanisms and interactions will help better understand the co-design aspects of microprocessor and parallel architectures, in the lab and in the classroom.