SBIR Phase II: An Ultra-High-Speed Cleaning Process for Electronic Device Manufacturing

这个小企业创新研究（SBIR）二期项目将开发从半导体晶圆上高速去除光刻胶的工艺技术，同时不损坏底层材料。这种工艺技术可以很容易地集成到现有的单晶圆湿式加工工具中。更小特征尺寸的高性能半导体器件的发展推动了铜和低k介电材料的采用，这些材料容易被传统的氧等离子体基抗蚀剂去除工艺损坏。虽然人们正在探索其他低温等离子体工艺作为低损伤替代方案，但明显较低的抗蚀剂去除率（1,000至2,000 A /min）是一个重大限制。为了应对这一挑战，该公司成功开发了一种新的臭氧-水基单晶片化学工艺，该化学工艺不会损坏低k介电材料，如黑金刚石（TM），也不会腐蚀铜。在第一阶段，该工艺实现了大于8000 A /min的蚀刻速率。第二阶段的研究将集中在将工艺硬件和工艺技术早期集成到商业单晶圆自旋处理系统中，进一步开发使用300毫米客户晶圆的工艺能力，并在客户现场放置三个系统进行评估。在商业上，这项研究计划的成功完成将最终开发出一种新的单晶圆工艺技术，用于制造特征尺寸小于90纳米的高密度半导体器件。几乎所有的新产能都是在尖端技术节点上制造300毫米晶圆。除了采用该技术的新晶圆加工设备每年直接销售6000万至1.2亿美元外，该项目还将使早期迁移到下一个技术节点所提供的生产力效益和单位制造成本降低。此外，这里开发的创新铜兼容清洁化学有望用于其他电子设备制造应用中的铜的无腐蚀清洁和表面处理。最后，这个过程使用了一种对环境无害的“绿色”化学。

This Small Business Innovation Research (SBIR) Phase II project will develop process technology for removing photoresist from semiconductor wafers at high speed while not damaging underlying materials. This process technology can be readily integrated into existing single wafer wet processing tools. The development of higher performance semiconductor devices with smaller feature sizes has driven the adoption of copper and low-k dielectric materials that are susceptible to damage by traditional oxygen plasma based resist removal processes. While other low temperature plasma processes are being explored as low damage alternatives, appreciably lower resist removal rates (1,000 to 2,000 A /min) are a significant limitation. In response to this challenge the company successfully developed a new ozone-water based single wafer process chemistry which does not damage low k dielectric materials such as Black Diamond (TM), and does not corrode copper. In phase I this process achieved an etch rate greater than 8,000 A /min. The phase II research will concentrate on the early integration of the process hardware and process technology into a commercial single wafer spin processing system, the further development of process capabilities using 300 mm customer wafers, and the placement of three systems at customer sites for evaluation.Commercially, the successful completion of this research program will culminate in the development of a new single wafer process technology for use in the manufacture of the high-density semiconductor devices with feature sizes below 90 nm. Nearly all of the new manufacturing capacity is built for 300 mm wafer fabrication at the leading edge technology node. In addition to direct sales of $60 to $120 million per year of new wafer processing equipment incorporating this technology, this project will enable the productivity benefits and reduction in unit manufacturing costs provided by the early migration to the next technology node. In addition, the innovative copper compatible cleaning chemistry developed here holds promise for corrosion free cleaning and surface treatment of copper in other electronic device manufacturing applications. Finally, this process uses an environmentally benign "green" chemistry.