MRI: ACQUISITION OF AN ULTRA FAST pS RF-TLP TESTING SYSTEM FOR ADVANCED VDSM ULSI RESEARCH TO NANO SCALE

该提案要求资金购买和建立一个超快PS RF-TLP测试系统集群，用于研究纳米级的VDSM IC，包括先进的超GHz RF/混合信号IC和片上ESD(静电放电)保护电路设计。智力优势：随着半导体技术进入VDSM ULSI体系，ESD故障成为一个主要的IC可靠性问题。片上ESD保护电路是保护IC芯片免受ESD破坏的关键，而超GHz射频IC的研究是未来无线通信的基础，而射频IC的设计和表征是一个巨大的挑战。PI在NSF和业界的资助下，在片上ESD保护和射频IC方面进行了开创性的研究，主要做了以下几个方面的工作：1.研究3D混合模式ESD模拟方法。2.开发准确的大电流ESD器件模型。3.开发全芯片ESD保护设计验证CAD软件。4.探索适用于亚100 nm超大规模集成电路的ESD保护方案。5.研究ESD现象及其对未来纳米技术的保护。6.探索超GHz硅射频集成电路和新兴宽带隙GaN半导体的ESD保护。7.开发用于射频SoC的超紧凑型IC电感。8.开发超GHz超宽带(UWB)SoC。9.研制26 GHz单片射频识别SoC。10.开发高性能ADC集成电路。高级高保真测试(1ps)对此类研究至关重要。新的超GHz RF-TLP测试系统集群由4012型CDM VSTLP测试仪和11971B型8英寸RF热晶片试探站组成。广泛影响：这一新系统将显著增强IIT的研究和教学基础设施。将开发新的课程和实验室。计划将多样性纳入研究和教学。该设施将向跨学科研究活动和外部用户开放，以促进跨学科和大学与行业在ESD保护和RF/混合信号IC方面的合作。

AbstractThe proposal requests funds to acquire and establish an Ultra-Fast pS RF-TLP Testing System Cluster for research on VDSM ICs down to nano-scale, including advanced super-GHz RF/mixed-signal ICs and on-chip ESD (electrostatic discharge) protection circuitry designs.Intellectual Merits: ESD failure becomes a major IC reliability problem as semiconductor technologies move into VDSM ULSI regime. On-chip ESD protection circuitry is required to protect IC chips against ESD damage, while Super-GHz RF IC research is the foundation to future wireless communications where design and characterization of RF ICs is a big challenge. The PI has been conducting pioneering research on on-chip ESD protection and RF ICs sponsored by NSF and the industry, with several thrusts: 1. To investigate 3D mixed-mode ESD simulation approach. 2. To develop accurate high-current ESD device models. 3. To develop whole-chip ESD protection design verification CAD software. 4. To explore ESD protection solutions for sub-100nm ULSI ICs. 5. To investigate ESD phenomena and protection for future nano-scale technologies. 6. To explore ESD protection for super-GHz silicon RF ICs and emerging wide-bandgap GaN semiconductors. 7. To develop super-compact IC inductors for RF SoC. 8. To develop super-GHz ultra wideband (UWB) SoCs. 9. To develop 26GHz single-chip RFID SoC. 10. To develop high-performance ADC ICs. Advanced hi-f testing (1ps) is critical to such research. The new Super-GHz RF-TLP Testing System Cluster consists of a Model 4012 CDM VSTLP Tester and a Model 11971B 8" RF Thermal Wafer Probing Station.Broader Impacts: This new System will significantly enhance the research and teaching infrastructure at IIT. New courses and laboratories will be developed. Integrating diversity into research and teaching is planned. The facility will be open to inter-disciplinary research activities and external users to promote cross-disciplinary and university-industry collaboration on ESD protection and RF/mixed-signal ICs.