CAREER CPA-CSA: Correctness-Constrained Execution for Processor Designs

当前微处理器系统的设计复杂性是这样的，以致于实际上每一个投放市场的系统都包含潜在的缺陷。制造商和设计公司都努力在系统开发期间尽可能多地验证和验证他们的设计，然后试图通过公开的勘误表报告来控制逃逸错误的影响。有些漏洞是无害的，可以通过BIOS或操作系统更新轻松克服，但还有一些漏洞对系统用户有潜在危险，或者可能危及系统的安全性并对系统性能产生不利影响。本项目致力于开发集成硬件和软件解决方案，以确保处理器芯片在设计有缺陷的情况下也能正常运行。推动这项研究的关键思想是为处理器创建两种操作模式：一种是在设计时已验证的系统部分内执行时使用的复杂高性能模式，另一种是在所有执行场景下保证正确的简单低性能模式。 通过在运行时仔细选择适当的操作模式，可以始终正确执行：当操作是在设计时验证的操作时，以高性能执行，否则以低性能执行。此外，由于低性能模式的极端简单性，可以保证该操作模式始终提供正确的结果，但性能价格。相关研究表明，在实践中，低性能模式只在非常罕见的情况下进行干预，因此其性能影响总体上可以忽略不计。 该项目所面临的研究挑战包括设计低成本的机制来选择快速和正确的模式之间的执行，开发简单的操作模式，以这样一种方式，可以充分验证，并开发技术，有效地编码正确的操作状态。

The design complexity of current microprocessor systems is such that practically every system released to the market incorporates latent bugs. Manufacturers and design houses alike strive to validate and verify their designs as much as possible during system development, and then attempt to contain the impact of escaped bugs through publicly available errata reports. Some escaped bugs are innocuous, and can be easily overcome through a BIOS or OS update, but still others are potentially dangerous to the users of the system, or they might compromise its security and adversely affect its performance.This project focuses on developing integrated hardware and software solutions to guarantee that a processor chip operates correctly, even if its design is flawed. The key idea driving this research is to create two modes of operation for the processor: a complex high-performance mode to be used when executing within the portion of the system that has been verified at design time, and a simple low-performance mode guaranteed to be correct under all execution scenarios. By carefully selecting the appropriate mode of operation at runtime, it is possible to always execute correctly: in high-performance when the operation is one that has been verified at design-time or in low performance otherwise. In addition, because of the extreme simplicity of the low-performance mode, it is possible to guarantee that this mode of operation always provides correct results but at a performance price. Related research has shown that, in practice, the low-performance mode intervenes only in very rare occasions, making its performance impact negligible overall. The research challenges to be undertaken in this project include devising low-cost mechanisms to select execution between fast and correct mode, developing the simple mode of operation in such a way that can be fully verified, and developing techniques to efficiently encode the correct states of operation.