CPA-CSA: Algorithms and Implementations for Scalable Transactional Memory

几年内，每台笔记本电脑/台式机/服务器的处理器都将是多核机器。为了使应用程序运行良好，它必须有效地并行化，以便在机器上的所有核心上执行。因此，芯片制造商必须提供架构，使程序员能够方便地将应用程序划分为多个并行线程。事务性内存（Transactional Memory， TM）编程模型被广泛认为是最著名的并发模型：它消除了死锁，在一般情况下提供高性能，并极大地简化了编程。它在研究会议上受到了极大的关注，也正在被纳入商业处理器。这种系统最大的开销之一是实现事务性语义所需的核心之间的通信。这种开销会显著影响未来处理器的性能和功耗。该项目不仅探索了减少所需通信量的算法，还探索了减少通信开销的机制。提出的工作背后的关键见解是，通过密切研究两者之间的相互作用，将最优片上网络和事务性内存实现融合在一起。在这项工作中开发的洞察力将导致更好的方法来计算最佳的片上网络。在研究过程中开发的模拟器和工具也将支持犹他大学的研究生和本科课程项目。

Within a few years, every laptop/desktop/server processor will be amulti-core machine. For an application to perform well, it must beefficiently parallelized to execute on all the cores on the machine.Chip manufacturers must therefore provide architectures thatmake it convenient for programmers to partition an application intomultiple parallel threads. The Transactional Memory (TM) programmingmodel is widely acknowledged to be the best known model forconcurrency: it eliminates deadlocks, provides high performance inthe common case, and greatly simplifies programming. It is receivinggreat attention in research conferences and is also being incorporatedin commercial processors. One of the biggest overheads for such asystem is the communication required between cores to implementtransactional semantics. This overhead significantly impactsperformance and power consumption of future processors. The project explores algorithms to not only reduce the required amount ofcommunication, but also explores mechanisms to reduce the overheadsof communication. The key insight behind the proposed work is that anoptimal on-chip network and transactional memory implementation willemerge by closely studying the interaction between the two. Theinsight developed during this work will lead to better methodologiesto compute an optimal on-chip network. The simulators and toolsdeveloped during the research efforts will also support projects ingraduate and undergraduate courses at the University of Utah.