CSR-PSCE, SM: Automatic Multithreaded and Transactional Memory Workload Synthesis for Efficient Multi-core Design Space Evaluation

从服务器到嵌入式计算市场，多核系统已经成为主流。由于硬件和软件设计人员采用事务性内存作为经济高效的多核编程范例，因此使用广泛的事务性应用程序评估TM/多核设计对于量化不同设计标准之间的权衡至关重要。TM/多核研究和设计界面临的一个障碍是缺乏具有代表性的事务内存基准。该项目旨在开发创新的技术、方法和新工具，以实现准确、有效和自动的事务性内存工作负载合成，以应对这些挑战。这对于多核架构的研究和设计社区来说是非常有益的。综合TM基准测试保留了原始多线程工作负载的行为，而参数化事务合成器可以生成具有多种行为的事务代码，这些行为可以有效地强调不同维度的TM设计。此外，参数化的合成工作负载将显著减少运行时，这允许架构师和设计人员快速探索大型TM/多核协同设计空间，在该空间中需要评估许多设计权衡。创新的事务性内存工作负载合成技术、方法和工具的成功开发将对未来多核系统的设计、评估和优化产生重大影响。具体来说，它将：(1)显著提高多核处理器和系统的设计和研究效率；(2)在很大程度上保证了该设计真正有利于面向多核的应用。该项目的综合教育和推广计划将有助于教育广泛的公民和学生。这包括用先进的建模和评估方法扩展计算机体系结构课程，招募少数民族和本科生参与研究，并与计算行业合作，将开发的技术整合到现实世界的多核处理器设计流程中。

Multi-core systems have become mainstream in everything from server to embedded computing markets. As hardware and software designers adopt transactional memory as a cost-effective multi-core programming paradigm, evaluating TM/multi-core design, using a wide spectrum of transactional applications, is crucial to quantify the trade-offs among different design criteria. One roadblock that the TM/multi-core research and design community faces is the lack of representative transactional memory benchmarks. This project aims to develop innovative techniques, methods, and new tools for accurate, effective, and automatic transactional memory workload synthesis to address these challenges. This may be significantly beneficial to the multi-core architecture research and design community. The synthetic TM benchmarks preserve the behavior of original multithreaded workloads while the parameterized transaction synthesizer can produce transactional code with widely varied behavior that can effectively stress the TM design in different dimensions. Moreover, the parameterized synthetic workloads will have significantly reduced runtime, which allows architects and designers to quickly explore the large TM/multi-core co-design space within which numerous design tradeoffs need to be evaluated. The successful development of innovative transactional memory workload synthesis techniques, methods and tools will have significant impact on the design, evaluation and optimization of future multi-core based systems. Specifically, it will: (1) significantly improve multi-core processor and system design and research productivity; and (2) largely ensure that the design is really beneficial to multi-core oriented applications. This project's integrated education and outreach plan will help to educate a broad spectrum of citizens and students. This includes expanding computer architecture curriculum with advanced modeling and evaluation methods, recruiting minorities and undergraduate students into research, and collaborating with the computing industry to integrate the developed technologies into real-world multi-core processor design flow.