CAREER: Design Automation for High-Performance Reconfigurable Computing

在异类执行模型中，通用处理器由专用协处理器加速。对于许多应用程序，此方法可以以相对较低的成本实现显著的性能改进。异构式计算面临的最大挑战是如何将任意程序与有效的协处理器体系结构相匹配。该项目研究了自上而下的设计自动化技术，用于分析现有软件并使其适应异构执行模型。当将科学软件适配到异构计算平台时，软件最昂贵的计算在协处理器上执行，协处理器通常是在现场可编程门阵列上实现的定制设计的体系结构。这种被称为核心的计算通常是众所周知的数值方法或信号变换。依赖于更奇特或晦涩难懂的算法的科学应用程序很少适用于异类执行。这样做的一个原因是，这样的应用程序可能没有定义良好的内核计算，这使得很难确定软件的哪些部分在映射到协处理器时将导致最高的整体性能改进。另一个原因是，手动设计执行复杂迭代行为的专用硬件需要高水平的设计工作，以及在硬件设计和目标应用程序的细节方面的高水平专业知识。为了解决这些问题，本研究开发了一套系统的技术，用于分析软件的运行时行为，以确定软件的哪些组件使用最少的输入和输出数据执行最多的计算。该分析的结果用于执行硬件/软件分区和解析动态存储器引用。在下一步中，编译器后端将生成精细并行化的协处理器体系结构。

In a heterogeneous execution model, a general-purpose processor is accelerated by a special-purpose co-processor. For many applications, this approach can yield significant performance improvement at a relatively low cost. The most significant challenge for heterogeneous computing is the task of matching an arbitrary program to an effective co-processor architecture. This project investigates top-down design automation techniques for analyzing and adapting existing software to the heterogeneous execution model.When adapting scientific software to a heterogeneous computing platform, the software?s most expensive computation is performed on the co-processor, which is usually a custom-designed architecture implemented on an FPGA. This computation, referred to as the kernel, is usually a well-known numerical method or signal transformation. Scientific applications that rely on more exotic or obscure algorithms are rarely adapted for heterogeneous execution. One reason for this is that such applications may not have a well-defined kernel computation, making it difficult to determine which portions of the software, when mapped to the co-processor, will result in the highest overall performance improvement. Another reason is that manually designing special-purpose hardware that performs complex, iterative behavior requires a high level of design effort as well as a high level of expertise in both hardware design and in the specifics of the target application. To address these problems, this research develops a set of systematic techniques for analyzing the runtime behavior of software to determine which components of the software perform the most computation using the least volume of input and output data. The results of this analysis are used to perform hardware/software partitioning and to resolve dynamic memory references. In the next step, a compiler back-end will generate a finely-parallelized co-processor architecture.