CIF: Imperfection-Resilient Scalable Digital Signal Processing Algorithms and Architectures Using Significance Driven Computation

当今的集成电路有望在功率预算不断减少的情况下提供高质量/高性能的水平。由于功率对电压的二次依赖关系，电源电压调节被认为是一种有效的降低功率的方法。然而，供应比例增加了所有计算路径中的延迟，并可能导致某些路径的计算不正确或不完整。除了功耗外，工艺变化也是技术扩展的一个主要设计问题。电源电压可以放大，或逻辑门可以放大，以防止延迟故障并实现更高的参数成品率。然而，这种技术是以增加功率和/或芯片面积为代价的。在纳米设计中，满足高产量、低功耗和高质量的矛盾要求正变得非常具有挑战性。因此，需要一种可扩展的设计方法，其中在不断变化的功率约束和工艺条件下实现最小的输出质量降级。此外，对于规定的功耗水平和工艺，设计方法必须考虑输入信号噪声和失真对数字信号处理(DSP)计算保真度的影响，并通过适当的算法和硬件设计确保在不同程度的噪声和失真下实现优雅的输出质量下降。这项研究涉及开发一种系统的方法，用于重新组织(转换)算法级计算、数据和底层硬件，以便在减少电源、增加工艺变化和降低输入信号质量的情况下实现最小的DSP系统性能降级。已经观察到，对于DSP应用/系统，所有计算在形成输出响应方面并不是同等重要的。调查人员利用这些信息来开发合适的算法/体系结构，以提供正确的？在输出质量与能源消耗(供应比例)与因工艺变化而产生的参数产量与输入信号噪声之间的权衡。为了解决对工艺变化的恢复能力，调查人员根据输出灵敏度确定这种系统的重要/不那么重要的组件。在这种情况下，在电源电压和/或参数变化按比例调整的情况下，如果某些路径中存在潜在的延迟故障，则只会影响不太重要的计算。换句话说，使用精心设计的算法和架构，调查人员为重要/不重要的计算元件提供不相等的误差保护(欠电压过定标)，从而在输出信号质量优雅下降的情况下实现功率消耗的大幅改善。

Present-day integrated circuits are expected to deliver high-quality/high-performance levels under ever-diminishing power budgets. Due to quadratic dependence of power on voltage, supply voltage scaling has been investigated as an effective method to reduce power. However, supply scaling increases the delays in all computation paths and can result in incorrect or incomplete computation of certain paths. Besides power dissipation, process variations also pose a major design concern with technology scaling. Supply voltage can be scaled-up or logic gates can be up-sized to prevent delay failures and to achieve higher parametric yield. However, such techniques come at the cost of increased power and/or die area. Meeting the contradictory requirements of high yield, low power and high quality are becoming exceedingly challenging in nanometer designs. Hence, there is a need for a scalable design methodology in which minimal output quality degradation is achieved under changing power constraints and process conditions. In addition, for a prescribed power consumption level and process, design methodology must take into account the effects of input signal noise and distortion on the fidelity of the Digital Signal Processing (DSP) computation and ensure that graceful output quality degradation is achieved under varying degrees of noise and distortion through proper algorithm and hardware design. The research involves development of a systematic methodology for reorganizing (transforming) algorithmic level computations, data and underlying hardware in such a way that minimum performance degradation in DSP systems is achieved under reduced power supply, increased process variations and reduced input signal quality. It has been observed that for DSP applications/systems, all computations are not equally important in shaping the output response. This information is exploited by the investigators to develop suitable algorithms/architectures that provide the ?right? trade-offs between output quality vs. energy consumption (supply scaling) vs. parametric yield due to process variations vs. input signal noise. To address resilience to process variations, the investigators identify the significant/not-so-significant components of such systems based on output sensitivities. Under such a scenario, with scaled supply voltage and/or parameter variations, if there are potential delay failures in some paths, only the less-significant computations are affected. In other words, using carefully designed algorithms and architectures, the investigators provide unequal error protection (under voltage over-scaling) to significant/not-so-significant computation elements, thereby achieving large improvements in power dissipation with graceful degradation in output signal quality.