SHF: Small: Energy Efficient Reconfigurable Logic for Ultra Low Power Ubiquitous Computing Systems

新兴的普适计算系统需要大量的小型无线节点集成到我们的环境中。为了在有限的能量下提供小尺寸和长寿命，这些节点必须使用超低功耗（ULP）电路，提供大量处理能力，提供灵活性以满足不同的应用需求，并允许低开发和部署成本。现有的电路设计方法，如asic、现成的部件或亚阈值处理器，无法同时提供所有这些特性。该项目正在开发一种节能的现场可编程门阵列（FPGA），能够运行到亚阈值电压区域，以提供满足普适计算系统需求的计算平台。商用fpga通常是为了与高性能处理器竞争而设计的，因此它们在高电压下工作，并使用不允许低电压亚阈值操作的电路结构。为了重新定位fpga在低电压下的节能运行，该项目用非缓冲单通晶体管开关取代了传统的可编程互连电路。这些开关在互连线上产生电压降，该电压降在可配置逻辑块的输入处使用异步感测放大器恢复。此外，开启互连开关的配置位单元的电压被提升。这个新的旋钮成倍地提高了速度，减少了亚阈值区域的变化，并且不会产生大量的能量开销，因为配置位单元只在FPGA重新编程时很少切换。重新设计了可配置逻辑块，以利用这种新的互连结构。该项目将导致FPGA能够高效节能的低电压操作。该FPGA器件将在普适计算应用中进行演示。由于它既低能耗又可重构，因此它将允许无处不在的计算节点采用大量处理从本地感知数据中提取信息，然后根据该信息做出决策，减少使用功率密集型无线电通信以延长节点寿命。FPGA的灵活性允许针对不同的应用或上下文需求快速重新定位节能硬件，提供一个新的计算平台，以增强软件和硬件开发人员创建无处不在的计算系统的能力。

Emerging ubiquitous computing systems require numerous small wireless nodes to be integrated into our surroundings. In order to provide both a small size and a long lifetime on limited energy, these nodes must use circuits that are ultra low power (ULP), offer substantial processing capabilities, provide flexibility to meet different application needs, and allow for low development and deployment costs. Existing approaches to circuit design such as ASICs, off the shelf parts, or sub-threshold processors fail to provide all of these traits at once. This project is developing an energy efficient field programmable gate array (FPGA) capable of operating into the sub-threshold voltage region to provide a computational platform that meets the needs of ubiquitous computing systems. Commercial FPGAs are usually designed to compete with high performance processors, so they operate at high voltages and use circuit structures that do not permit low voltage sub-threshold operation. To re-target FPGAs for energy efficient operation at low voltage, this project replaces conventional programmable interconnect circuits with non-buffered single pass-transistor switches. These switches create a voltage drop in the interconnect lines that is recovered using asynchronous sense amplifiers at the inputs to configurable logic blocks. Furthermore, the voltage of the configuration bit cells that turn on the interconnect switches is boosted. This new knob increases the speed exponentially and reduces variations in the sub-threshold region and does not incur substantial energy overhead since the configuration bit cells only switch rarely when the FPGA is reprogrammed. The configurable logic blocks are re-designed to take advantage of this new interconnect fabric. This project will result in an FPGA capable of energy efficient low voltage operation. The FPGA device will be demonstrated in ubiquitous computing applications. Since it is both low energy and reconfigurable, it will allowubiquitous computing nodes to employ substantial processing to extract information from locally sensed data and then make decisions based on that information, reducing use of power intensive radio communication to extend the node lifetimes. The flexibility of the FPGA allows rapid re-targeting of the energy efficient hardware for different application or contextual requirements, providing a new computing platform to enhance the ability of software and hardware developers to create ubiquitous computing systems.