TC: Small: A Secure Trojan-Resistant Application-Specific Integrated Circuit Architecture

半导体行业的全球化和水平分层加剧了集成电路制造供应链妥协的威胁。具体地说，知识产权盗窃、未经授权的生产和硬件特洛伊木马插入是令人严重关注的问题。此外，先进的半导体制造设备和专业技术的激增使该领域中针对集成电路的新型攻击成为可能。最近，通过利用无意中的信息泄露来绕过加密算法的理论优势的旁路攻击被证明是特别有效的，同时只需要适度的预算和专业知识。大多数现有的对策是将安全功能改造到现有的设计流程上，而不是从头开始内置安全功能。该项目开发了一种全新的专用集成电路(ASIC)体系结构，旨在抵抗硬件特洛伊木马插入，并具有低侧信道信息泄漏，同时仍可实现高性能、低功耗、紧凑面积和未来的可扩展性。该体系结构由实现为只读存储器(ROM)查找表(LUT)的逻辑门阵列组成，这些查找表通过可重构网络互连。只读存储器LUT以低旁路发射实现高效操作，且由于其规则结构而具有高度可扩展性。可重新配置的互连实现了设计混淆、生产计量以及完全的内部节点可观察性和可控性，以便检测硬件特洛伊木马。该体系结构的本质阻止了木马插入，并实现了非破坏性的制造后特洛伊木马检测。该体系结构广泛适用于从微处理器到ASIC的各种IC，这些IC需要能够安全运行的高效设计

Globalization and horizontal stratification of the semiconductor industry has exacerbated the threat of a compromise in the integrated circuit manufacturing supply chain. Specifically, intellectual property theft, unauthorized production, and hardware Trojan horse insertion are of significant concern. Further, the proliferation of advanced semiconductor fabrication equipment and expertise has enabled novel attacks against integrated circuits in the field. Recently, side-channel attacks that bypass the theoretical strength of cryptographic algorithms by exploiting inadvertent information leakage have shown to be particularly effective while requiring only a modest budget and expertise. Most extant countermeasures retrofit security features onto existing design flows, rather than build-in security from the ground up. This project develops a novel application-specific integrated circuit (ASIC) architecture designed from the ground up to resist hardware Trojan horse insertion and have low side-channel information leakage, while still achieving high performance, low power, compact area, and future scalability. The architecture consists of an array of logic gates implemented as read-only memory (ROM) look-up tables (LUTs) interconnected by a reconfigurable network. The ROM LUTs achieve efficient operation with low side-channel emissions and are highly scalable due to their regular structure. The reconfigurable interconnect enables design obfuscation, metering of production, and complete internal node observability and controllability in order to detect hardware Trojans. The very nature of the architecture deters Trojan insertion and enables non-destructive post-manufacturing Trojan detection. The architecture has wide applicability across a range of ICs, from microprocessors to ASICs, that require efficient designs capable of secure operation