PFI-BIC: Novel Circuit Architectures and Design Methodologies for Low Power Digital Systems

亚利桑那州立大学的创新合作项目旨在开发一种新的数字系统设计方法，以便在不降低运行速度的情况下显著降低数字系统的功耗和尺寸。如果成功，这项研究的结果可以用于提高几乎所有数字系统的能源效率，包括台式电脑、笔记本电脑、平板电脑、手机和其他手持数字设备。这种新方法采用阈值逻辑门，其计算逻辑函数的方式与传统逻辑门的操作方式明显不同。阈值逻辑门在单个原始单元中实现复杂的逻辑功能，否则将需要许多传统逻辑门的网络。正是将逻辑吸收到单个单元中，这是功率和尺寸减小的原因。提出了一种新的阈值逻辑门结构，称为差分阈值逻辑锁存器（DTLL），作为原始逻辑单元。DTLL单元与现有的逻辑门兼容，可用于取代数字电路的某些部分，以减少其功率和面积，并可能提高其速度。由此产生的电路将是一个混合电路，由DTLL单元和传统逻辑门组成。该方法的一个显著优点是，DTLL单元可以像标准单元一样高效地实现，从而可以将阈值逻辑技术与现有的专用集成电路（ASIC）设计方法集成在一起。为了实现阈值逻辑与传统ASIC设计的集成，需要开发设计基础设施，其中包括阈值单元库的设计，以及将现有数字设计转换为混合设计的大量算法和软件工具。这个项目将建设这样一个基础设施。该项目的更广泛影响将有利于移动电子应用程序的性能，如智能手机，相机，笔记本电脑等。这些设备将从该项目带来的功耗降低中获益最多。本项目采用的降低功耗的方法的一个基本优势是阈值逻辑技术与现有逻辑兼容。因此，所提出的方法与现有的工业设计方法完全兼容。不需要新的制造技术，现有的商业后端设计工具（例如，合成、优化、放置和布线）可用于混合网表。项目启动时的合作伙伴：知识增强合作伙伴（KEP）；牵头机构：亚利桑那州立大学（Ira A. Fulton工程学院和计算、信息与决策系统工程学院）；小型企业：Cactus Semiconductor Inc.和Everspin Inc.。其他合作伙伴-大型企业：高通和德州仪器。

This Partnership for Innovation project from Arizona State University is aimed at developing a new approach to digital system design in order to significantly reduce the power consumption and size of digital systems without reducing their speed of operation. If successful, the results of this research can be used to improve the energy efficiency of nearly every digital system, including desktop computers, laptops, tablets, cell phones and other handheld digital devices. This new approach employs threshold logic gates, which compute logic functions in a manner that is distinctly different from the way conventional logic gates operate. A threshold logic gate implements a complex logic function in a single primitive cell, which would otherwise require a network of many conventional logic gates. It is this absorption of logic into a single cell that is the reason for the reduction in power and size. A novel architecture for a threshold logic gate, called a differential threshold logic latch (DTLL), is proposed as the primitive logic cell.DTLL cells are compatible with existing logic gates, and can be used to replace parts of a digital circuit to reduce its power and area and possibly improve its speed. The resulting circuit will be a hybrid, consisting of DTLL cells and conventional logic gates. A significant advantage of the proposed approach is that DTLL cells can be implemented as efficiently as standard cells, making it possible to integrate threshold logic technology with existing Application Specific Integrated Circuit (ASIC) design methodology. To enable the integration of threshold logic with conventional ASIC design requires the development of design infrastructure, which includes the design of a threshold cell library, and a host of algorithms and software tools that transform existing digital designs into hybrid designs. This project will build such an infrastructure.The broader impacts of the project will be benefits to performance of mobile electronic applications such as smart phones, cameras, laptops, etc. These devices will benefit the most from a reduction in power consumption delivered as a result of this project. A fundamental advantage of the approach taken in this project to reducing power consumption is that the technology of threshold logic is compatible with existing logic. As a result, the proposed approach is fully compatible with existing industrial design methodology. No new fabrication technology will be required, and existing commercial back-end design tools (e.g., synthesis, optimization, placement and routing) can be used for the hybrid netlists.Partners at the inception of the project: the knowledge enhancement partners (KEP): Lead institution: Arizona State University (Ira A. Fulton Schools of Engineering and School of Computing, Informatics and Decision Systems Engineering); and Small Businesses: Cactus Semiconductor Inc. and Everspin Inc. Other Partners--Large Businesses: Qualcomm and Texas Instruments.