SHF: Small: Memory Consistency -- Hardware, Compiler, and Programming Support

多核机器的出现使得通过并行性为广泛的应用程序提供高性能成为可能。虽然这种机器已经无处不在，但它们对软件开发人员构成了重大挑战。其中一个挑战是处理商业多核机器支持的宽松内存一致性模型。同时交付高性能和确保程序正确性需要在代码中小心地引入fence指令。过度使用fence指令会导致性能差，而忽略它们会导致不正确的程序行为。本研究将探讨限制fence指令范围的方法，以尽量减少其对性能的影响，同时保留所需的程序行为。在现有系统中，硬件不知道作用域，因此fence实现强制执行跨fence的严格内存访问顺序，从而导致不必要的停顿。将开发推断作用域信息的替代方法，以约束由硬件强制执行的内存顺序。特别是硬件、编译器和编程支持的开发。本研究开发的软件和硬件技术将提供给其他研究人员，以便他们能够进行实验。本研究课题与商用处理器制造商有关。参与本研究的学生将获得多核系统设计和编程方面的宝贵训练。

The advent of multicore machines has enabled delivery of high performance via parallelism for a wide range of applications. While such machines have become ubiquitous, they pose significant challenges for software developers. One challenge is dealing with the relaxed memory consistency models supported by commercial multicore machines. Simultaneously delivering high performance and ensuring program correctness requires careful introduction of fence instructions in the code. Excessive use of fence instructions leads to poor performance while their omission of can lead to incorrect program behavior.This research will investigate means for constraining the scope of a fence instruction to minimize its impact on performance while preserving desired program behavior. In existing systems the hardware is unaware of the scope and hence fence implementations enforce a strict ordering of memory accesses across a fence that leads to unnecessary stalls. Alternative means for inferring the scope information will be developed for constraining the memory orderings enforced by the hardware. In particular, development of hardware, compiler, and programming support will be carried out. The software and hardware techniques developed in this research will be made available so other researchers are able to experiment with them. The subject of research is relevant to commercial processor manufacturers. The students involved in this research will receive valuable training in the design and programming of multicore systems.