EAGER: Monolithic 3D Integration of Resistive Random Access Memory (ReRAM): A Technological Exploration

随着大数据的快速增长，需要下一代非易失性存储技术来实现大容量和快速带宽。电阻随机存取存储器(ReRAM)技术是突破当今闪存技术规模限制的新兴候选技术之一。ReRAM技术的研究和开发将使当今几乎所有可用的数字设备受益，从消费电子产品到企业电子产品。它还可能催生涉及亿级数据计算的新应用，例如数据挖掘、机器学习和生物信息学等，从而使整个半导体行业受益。学生暑期实习计划与行业合作伙伴一起进行，这对拓宽学生的知识和技能将是无价的。这项研究开发的工具和技术将用于亚利桑那州立大学新开发的存储器设计研讨会课程。PI将使模拟器工具可供其他教育工作者、研究人员和行业从业者使用。研究成果的传播还将通过会议教程、小组讨论和讲习班进行。将共同努力，让代表性不足的群体和本科生参与这项研究，并促进K-12学生主修科学和工程。这项提议旨在解决ReRAM单片3D集成的基本技术挑战。虽然ReRAM技术在单元级表现出非常有吸引力的特性，但在阵列级，其较低的集成密度限制了其相对于主流NAND Flash技术的经济竞争力。该项目研究了使用ReRAM的单片3D集成作为实现超高密度交叉点存储器架构的一种有前途的方法。建议的研究活动侧重于器件级工程，设计目标从电路级阵列建模，旨在实现3DReRAM技术的大规模集成。将开发可评估集成密度、每位成本、读/写裕度、访问延迟和功率/能量消耗的阵列宏模型，并通过SPICE模拟对其进行校准。3D ReRAM的器件原型将按照阵列宏模型所给出的期望目标进行制造和优化。所有设备工程活动将利用电极/氧化物界面工程和氧化物/氧化物界面工程的现有知识，并进一步有助于对相关问题的新理解。

With the rapid growth of big data, next generation non-volatile memory technologies are needed to enable a large capacity and fast bandwidth. The resistive random access memory (ReRAM) technology is one of the emerging candidates beyond the scaling limit of today's FLASH technology. The research and development of the ReRAM technology will benefit nearly every digital device available today from consumer electronics to enterprise electronics. It may also spawn new applications involving the computation on the exascale of data, e.g. data mining, machine learning, and bio-informatics etc. thus benefitting the semiconductor industry at large. Student summer internships are planned with the industrial partners, which will be invaluable for broadening the knowledge and skills of the students. The tools and techniques developed in this research will be used in the newly developed seminar course on memory design at ASU. The PI will make simulator tools available for use by other educators, researchers, and industry practitioners. Dissemination of research findings will also be carried out through conference tutorials, panel discussions, and workshops. A concerted effort will be made to involve underrepresented groups and undergraduate students in this research, and also to promote the K-12 students to major in science and engineering. This proposal aims to tackle the fundamental technological challenges for the monolithic 3D integration of ReRAM. Although the ReRAM technology shows very attractive characteristics at single cell level, at the array level its lower integration density limits its economical competiveness over the mainstream NAND FLASH technology. The project examines the use of monolithic 3D integration of ReRAM as a promising approach for enabling ultra-high density cross-point memory architecture. The proposed research activities focus on the device-level engineering with the design targets from the circuit-level array modeling, aiming at enabling the large-scale integration of 3D ReRAM technology. Array macro model that can assess integration density, cost per bit, read/write margin, access latency, and power/energy consumption will be developed and calibrated by SPICE simulation. Device prototypes for 3D ReRAM will be fabricated and optimized towards the desired targets given by the array macro model. All device engineering activities will leverage the existing knowledge of the electrode/oxide interface engineering and oxide/oxide interface engineering and further contribute to new understandings of relevant issues.