SHF:Small: Reducing Test Time and Improving Diagnosis for Increasingly Dense ICs

随着技术的发展，测试和诊断集成电路所需的数据量继续急剧增长，这不仅是因为更大的设计，还因为需要针对新缺陷进行额外的测试。集成电路的密度继续以比自动测试设备（ATE）和被测芯片之间的测试数据带宽更快的速度增长，这受到测试仪上的通道数量和芯片上的引脚数量的限制。该项目涉及开发与现有技术根本不同的数据压缩和提取新方法，能够更有效地减少数据量，显著提高测试时间和诊断准确性。该项目将为研究生和本科生，包括来自代表性不足群体的学生，提供最新设计和测试技术方面的高级培训。本项目将探讨改进试验数据压缩和提取的几个新的研究方向。一个根本的新方法，提取信息从线性签名使用符号取消将研究寻找错误的位置，以帮助诊断。通过将信号信息与电路结构信息相结合，可以提高诊断精度。测试压缩的改进将通过新的概念来实现，包括(i)测试刺激解压和输出响应压缩之间的带宽共享，（ii）结合线性和非线性编码，（iii）低扇出响应压缩架构，以及（iv）从线性压缩器中动态提取。本项目开发的新技术和体系结构将得到实施，并对其性能进行评估。

The amount of data required to test and diagnose integrated circuits continues to grow dramatically as technology scales, not only because of larger designs, but also the need for additional tests to target new defects. The density of ICs continues to grow faster than the test data bandwidth between automatic test equipment (ATE) and the chip-under-test, which is constrained by the number of channels on the tester and pins on the chip. This project involves developing new approaches for compression and extraction of data that are fundamentally different from existing techniques and capable of more efficiently reducing the amount of data and significantly improving test time and diagnosis accuracy. The project will provide advanced training to both graduate and undergraduate students, including those from underrepresented groups, in the latest design and test technologies.Several new research directions for improving compression and extraction of test data will be investigated in this project. A fundamentally new approach for extracting information from linear signatures using symbolic canceling will be studied for finding error locations to aid in diagnosis. By combining information from the signature together with structural information from the circuit, much greater diagnostic precision is possible. Improvements in test compression will be pursued through new concepts including (i) bandwidth sharing between test stimulus decompression and output response compaction, (ii) combining linear and non-linear encoding, (iii) low fan-out response compaction architectures, and (iv) dynamic extraction from linear compactors. The new techniques and architectures developed in this project will be implemented and their performance evaluated.