SHF: SMALL: Collaborative Research: Reconfigurable and Programmable Processor Architectures for Brain-Computer Interfacing

脑机接口(BCI)的主要动机之一是恢复因中风或慢性病而无法通过正常神经通路移动或交流的患者的行为功能。要恢复瘫痪患者的全方位运动，需要从相对较大的脑神经元群体进行记录。无线传输大量神经数据以便在计算机上进行离线处理会造成与热相关的组织损伤，并阻碍假肢的实时控制。在这项SHF合作研究中，为在使用脑植入电子设备进行实时神经信号处理和在机器或计算机上进行离线处理的无线数据传输之间找到最佳平衡奠定了基础，从而使脑植入集成电路的总功率/能量消耗最小。这项研究的重点是一种变革性的BCI专用处理器架构，利用定制的数字电路来大幅放松耗电的无线数据传输，同时实时控制假肢。研究成果对教育和社会的影响包括：利用新的“大脑芯片”推广计划，扩大未被充分代表的高中生的参与；通过“家庭实验室”的方法加强教育学习；通过圣地亚哥残疾中心的研讨会，让当地社区和更广泛的社会参与进来，尤其是残疾人；并为数百万患有神经退行性疾病或瘫痪的患者的康复和提高生活质量做出贡献。这项研究创造了一种混合处理器，它既可通过软件编程来高效执行神经信号处理算法，又可通过硬件重新配置来采用可配置的指令集架构(ISA)。软件可编程性支持方法和算法改进的持续发展，同时利用较低的硅面积。与映射到固定处理器体系结构上的优化算法不同，该处理器在运行时通过采用可配置的ISA而不是固定和预定的指令集来优化匹配BCI算法的特定要求，从而获得更高的能效。该处理器还利用各种专用硬件架构，包括人工神经网络和尖峰神经网络，对神经信号进行面积和能量高效处理，仅将翻译后的命令直接传输到假肢设备，从而将无线通信开销降至最低。为了寻找和评估在脑植入处理器上实时操作的候选神经信号处理算法，这项多学科研究通过基于软件的性能和精度分析工具，促进了对神经信号处理的大设计空间的搜索，该工具将可靠地测量它们的重要特征。通过使用有意义的效率和精度指标对潜在的神经信号处理算法进行量化比较，BCI专用处理器和专用硬件架构将针对节能操作进行优化。混合处理器架构和设计规格通过在华盛顿大学华盛顿国家灵长类研究中心的猕猴身上测试BCI系统进行了优化。该奖项反映了NSF的法定使命，并通过使用基金会的智力优势和更广泛的影响审查标准进行评估，被认为值得支持。

One of the primary motivations of brain-computer interfaces (BCIs) is to restore behavioral functions for patients who are unable to move or communicate through normal neural pathways because of strokes or chronic diseases. Restoring a full range of movements for paralyzed patients requires recordings from a relatively large population of brain neurons. Wireless transmission of large amounts of neural data for off-line processing on a computer imposes heat-related tissue damage and hinders real-time control of the prosthetics. In this SHF collaborative research, a foundation is laid for finding an optimal balance between real-time neural-signal processing using a brain-implantable electronic device and wireless data transmission for offline processing on a machine or computer so that the total power/energy consumption of the brain-implanted integrated circuit is minimized. This research focuses on a transformative BCI-specific processor architecture utilizing custom digital circuits to drastically relax power-hungry wireless data transmission while controlling prosthetics in real-time. The impact of research findings on education and society include: broadening the participation of underrepresented high school students using the new "Brain Chips" outreach program; enhancing educational learning via the "lab-at-home" approach; engaging the local community and broader society, especially those with disabilities, via workshops at the Disability Center San Diego; and contributing to rehabilitation and improving the quality of life of millions of patients suffering from neurodegenerative diseases or paralysis.This research creates a hybrid processor that is both software-programmable to efficiently execute neural-signal processing algorithms and hardware-reconfigurable to adopt a configurable instruction set architecture (ISA). The software-programmability supports the continuing evolution of approaches and algorithmic improvements while utilizing lower silicon area. Rather than optimized algorithms mapped onto a fixed-processor architecture, the processor optimally matches the specific requirements of the BCI algorithms at runtime by adopting a configurable ISA instead of a fixed and predetermined set of instructions and hence attains greater energy efficiency. The processor also utilizes various dedicated hardware architectures, including artificial and spiking neural networks, for area and energy-efficient processing of neural signals, transmitting only the translated commands directly to prosthetic devices and thus, minimizing the wireless communication overhead.To find and assess candidate neural-signal processing algorithms for real-time operation on the brain-implantable processor, this multidisciplinary research boosts the search in the large design space of neural-signal processing via a software-based performance and accuracy analysis tool that will reliably measure their important characteristics. By quantitatively comparing the potential neural-signal processing algorithms using meaningful efficiency and accuracy metrics, the BCI-specific processor and dedicated hardware architectures will be optimized for energy-efficient operation. The hybrid processor architecture and the design specifications are optimized by testing the BCI system at the Washington National Primate Research Center at the University of Washington in macaque monkeys.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.