Highest-Linearity Nyquist Rate SAR ADCs in nm-CMOS - NanoSAR

传感器读出和医疗应用中的多路复用操作需要具有高分辨率的奈奎斯特速率模数转换器（adc），其中对于数字锁定检测等任务而言，最高线性度至关重要。虽然SAR adc在纳米级CMOS技术中以其卓越的功率效率而闻名，但除非使用技术（过采样，噪声整形等），否则它们显示出有限的有效分辨率和线性度，这再次阻止奈奎斯特速率，无内存操作。因此，高分辨率ADC设计的最新技术是由过采样转换器主导的，对于奈奎斯特速率操作，必须付出巨大的功率代价。在该项目提案的第一阶段，研究了一种新的架构，该架构将本质线性sigma-delta (SD) DAC结合到SAR ADC中，以省略具有良好匹配的巨大电容性DAC (CDAC)；对于奈奎斯特速率操作，SD DAC以增量方式操作。然后研究了一种首选实现，即DAC在功能上分为粗CDAC，也用作采样电容器，以及用于精细转换步骤的本质线性增量SD (I-SD) DAC。结果是一个40纳米CMOS的SAR ADC，它实现了有史以来最高的线性度，同时在最小的报道面积上实现了卓越的功率效率。在第二个项目阶段，激励目标是在架构层面上进一步改进，以使I-SD DAC增强型SAR ADC能够以更高的速度运行。因此，进一步分析了粗CDAC和精细I-SD DAC的分裂，并评估了I-SD DAC是否最终只能用作校准引擎；另外，分析了I-SD DAC更快的运行速度。此外，基于令人大开眼界的vco结构的新型混合比较器通过将其相位噪声建模为比较器的等效输入参考幅度噪声来增强，其次通过研究是否可以通过多值而不是二进制方式提取相位差来使用多位运算。由于新架构属于模拟设计领域，为了向电路设计者证明新架构的优越性能，有必要进行电路实现。因此，首选概念将在40nm CMOS技术中实现，通过重复使用尽可能多的先前设计的电路来减少设计时间。

Nyquist-rate analog-to-digital converters (ADCs) with high resolution are needed for multiplexed operation in sensor readouts and medical applications, where for tasks such as digital lock-in detection highest linearity is of prime importance. While SAR ADCs are well known for their superior power efficiency in nanoscaled CMOS technology, they show limited effective resolutions and linearity unless techniques are used (oversampling, noise-shaping, etc) which again prevent Nyquist-rate, memoryless operation. The state of the art in high-resolution ADC design is thus dominated by oversampled converters, and for Nyquist-rate operation a significant power penalty has to be paid. In the first phase of this project proposal, a new architecture was investigated which combined an intrinsically linear sigma-delta (SD) DAC into a SAR ADC in order to omit huge capacitive DACs (CDAC) with good matching; for Nyquist rate operation the SD DAC was operated in incremental fashion. A preferred implementation was then investigated, were the DAC is functionally split into a coarse CDAC, serving also as sampling capacitor, and an intrinsically linear incremental SD (I-SD) DAC for the fine conversion steps. The outcome was a SAR ADC in 40nm CMOS, which achieved the highest ever reported linearity while achieving superior power efficiency on the smallest reported area for such resolution. In the second project phase, the motivating goal is to establish further improvements on architectural level, in order to enable the I-SD DAC enhanced SAR ADC to operate at much higher speed. Therefore, the splitting of the coarse CDAC and fine I-SD DAC is further analysed, and it is also evaluated if the I-SD DAC can be ultimately used as calibration engine only; alternatively, much faster operating speed of the I-SD DAC is analysed.Moreover, the new hybrid comparator based on an eye-opening, VCO-structure is enhanced both by modelling its phase noise as equivalent input referred amplitude noise of the comparator, and secondly by investigating, if multibit operation can be used by extracting the phase difference in multivalued rather than binary fashion. Since the new architectures belong to the field of analog design, a circuit implementation is necessary in order to prove the superior performance of the novel architectures to the circuit designers community. Therefore, the preferred concept will be implemented in a 40nm CMOS technology by reusing as many of the previously designed circuitry as possible to reduce design time.