Efficient Power Amplifiers for Aggressive Duty-Cycling(EPAAD)

未来毫米波通信的能耗必须降低。峰值数据速率仅在短时间内需要。人工智能（AI）启发的自适应占空比提供持续时间低至亚μs范围的数据包对于节省能源非常有吸引力。休眠时间可以比活动操作时间长> 10000倍。后者可以在与DC操作点切换（OPS）时间类似的范围内或者甚至更小。因此，总能量消耗不仅由活动操作确定，而且由睡眠和OPS状态确定。在收发器中，DC功率的主要部分由功率放大器（PA）汲取。发表了大量的作品，处理PA在主动操作中能量效率的降低。直到今天，很少有人关注在睡眠和OPS状态期间消耗的PA能量的最小化。为了为新型超高效积极的工作循环铺平道路，EPAAD探索了最大限度地减少OPS和睡眠能量的方法。由于可以选择以最小的DC开销进行超短数据突发，因此可以节省能量。采用E类功率放大器还可以将有源操作的能量保持在尽可能低的水平。OPS时间主要由与处理电源电流变化的馈电电感、控制节点、PA核心、LC阻抗匹配、RF接地分流和AC耦合电容相关的时间常数决定。为了降低馈电电感和相关的时间常数，我们采用了逆E类架构。类共源共栅晶体管堆叠降低了PA内核的米勒效应和RC常数。差分拓扑结构可最大限度地减少RF分流电容器所需的尺寸和延迟。为了最小化休眠模式中的泄漏，共源极级的栅极电压必须被下拉，从而导致更大的OPS持续时间。上栅极的切换同时保持下栅极处于高电平导致较低的OPS时间。因此，我们研究新的控制方案与堆叠晶体管的顺序开关，以减少OPS和睡眠能量。为了验证这些方法，在22 nm FDSOI CMOS上设计了一个28 GHz的功率放大器. Globalfoundries为我们提供了未发布的晶体管，其目标是领先的品质因数，漏源极击穿电压为4.2 V，同时仍然提供高达250 GHz的最高振荡频率。关键的定量PA目标是记录开/关OPS时间< 10 ns、睡眠漏电流< 500 nA、RF输出功率> 24 dBm和40%的功率附加效率（PAE）。对于这项研究，DFG资金是由德累斯顿工业大学的Frank Ellinger申请的。基于这些见解，哥伦比亚Pontificia Universidad Javeriana（PUJ）的Méndez教授执行了关于全收发器基于仿真的能量和性能调查的其他任务。

The energy consumption of future millimetre-wave communications has to be reduced. Peak data rates are only required during a short duration. Artificial intelligence (AI) inspired adaptive duty-cycling providing data packages with duration down to the sub-μs range is very attractive to save energy. The sleep times can be > 10 000 times longer than the active operation times. The latter can be in a similar range or even smaller than the DC operation point switching (OPS) times. Thus, the overall energy consumption is not only determined by the active operation but also by the sleep and OPS states. In transceivers, a major part of the DC power is drawn by the power amplifiers (PAs). A huge number of works were published treating the reduction of the PA energy efficiency in active operation. Until today, much less attention was spent on the minimization of the PA energy consumed during the sleep and OPS states. To pave the way for a new class of ultra-efficient aggressive duty-cycling, EPAAD explores approaches to minimize the OPS and sleep energies. Due to the option to go for ultra-short data bursts at minimum DC overhead, energy can be saved. Class-E PAs are employed to keep also the energy for active operation as low as possible. The OPS times are mainly determined by the time constants associated with the feeding inductance handling the supply current change, control nodes, PA core, LC-impedance matching, RF-ground-shunt and AC-coupling capacitors. To reduce the feeding inductance and the associated time constant, we go for an inverse class-E architecture. Cascode-like transistor stacking reduces the Miller effect and the RC constant of the PA core. A differential topology minimizes the required sizes and delays of the RF-shunt capacitors. To minimize the leakage in sleep mode, the gate voltage of the common source stage has to be pulled down leading to a larger OPS duration. The switching of the upper gates while keeping the lower gate at high level results in lower OPS times. Hence, we investigate novel control schemes with sequential switching of stacked transistors to reduce both the OPS and sleep energies. To verify the approaches, a 28 GHz PA is designed in 22 nm FDSOI CMOS. Globalfoundries offers us non-released transistors targeting a leading-edge figure of merit with drain source breakdown voltage of ≈ 4.2 V while still providing a high maximum frequency of oscillation of ≈ 250 GHz. Key quantitative PA goals are record on/off OPS times < 10 ns, sleep leakage currents < 500 nA, an RF output power > 24 dBm and 40 % power added efficiency (PAE). For this research, DFG funding is requested by Frank Ellinger at TU Dresden. Based on these insights, additional tasks regarding simulation-based energy and performance investigations of full transceivers are performed by Prof. Méndez from Pontificia Universidad Javeriana (PUJ) in Columbia.