The Development of Basic Software Techniques for Variable-Voltage Processors Targeting Low-Energy Consumption

本文讨论了实现低功耗设计的变压处理器软件的一些基本技术，以及建模技术，并通过仿真评估了它们的潜在效益。1)提出了一种基于可变电压处理器的实时系统任务调度技术，利用该技术可以动态改变电源电压。2)搭建了软核处理器数据路径宽度优化平台，并利用MPEGAAC解码器对提出的数据路径优化方法进行了评估。此外，还提出了一种基于数据路径宽度优化的能量最小化方法。为了在设计的早期阶段找到给定应用程序的最佳数据路径宽度，还提出了一种基于有效位宽和变量访问频率的性能评估技术。3)提出了一种新的兼顾计算精度、目标面积和功耗的数据路径宽度优化方法。4)提出了一种通过减少冗余位切换来降低功耗的方法，其中数据总线上的有效位线称为有效位，另一位称为冗余位。5)建立了片上系统(SoC)的成本模型，其中每个成本都是一个参数，并给出了一种根据市场规模和产品数量进行设计的方法。6)提出了一种适用于合并DRAM/Logic LSI的高性能/低功耗高速缓存结构，其缓存线大小可变；此外，还提出了一种利用程序执行足迹的低功耗指令高速缓存体系结构。

This work discusses some basic techniques of software for variable-voltage processors in order to realize low-energy design, together with modeling techniques and evaluations of their potential benefits by simulation. Details are listed as follows :1) A task scheduling technique for a real-time system with a variable-voltage processor, by which supply voltage is changed dynamically, is presented.2) A platform for datapath width optimization of soft-core processors is built and the presented methodology of datapath optimization is evaluated by using MPEG AAC decoder. In addition, an energy minimization methodology using datapath width optimization is proposed. To find the optimized datapath width for a given application in the early phase of designs, an effective bitwidth and access frequency of variables based performance estimation technique is also developed. A low-energy memory design technique is presented as well.3) A new datapath width optimization methodology considering computation precision targeting area and power reduction is presented.4) A power reduction technique by reducing switching of redundant bit is presented, here effective bit line on data bus is called active bit, the other bit is called redundant bit.5) A cost model for SoC (System on a Chip), in which each cost as a parameter is presented, and a design method by market scale and number of products is also presented.6) High-performance/low power cache architectures with variable cache-line size for merged DRAM/Logic LSIs are presented ; in addition, a low-power instruction cache architecture exploiting program execution footprints is presented.