Continuous Atomic-Layer Deposition of Metal Gate/High-k Metal Oxide Gate Dielectric Stack Structure

到2001财年为止，用(ZTb：Zr(t-OC_4H_9)_4)和H_2O研究了用于下一代栅电介质的ZIO_2的原子层沉积(ALD)。此外，通过ALD在硅衬底上沉积了超薄的氮化硅层作为界面层的阻挡层。然后在AlD氮化硅上沉积AlD-ZIO_2，形成叠栅结构。AlD氮化硅层成功地抑制了SiO_2界面层的形成。在2003财政年度，对薄膜的生长进行了更详细的研究，以检查薄膜质量和ALD机理。研究了电容器的漏电流特性，发现ALDZrO2/AlD氮化硅叠层栅介质和ALDZrO2栅介质的漏电流都是由直接隧穿引起的。此外，为了抑制多晶硅栅和栅介质之间的界面反应，还考察了利用AlD在ZrO2上形成氮化硅的可能性。另一方面，由于HfO_2是未来高k栅电介质最有希望的候选者，因此采用Hf(HfAcAc)_4和H_2O交替曝光的方法来考察HfO_2的可能性。然而，无法获得质量良好的薄膜。采用AlD氮化硅栅介质(EOT=2.3 nm)制备了N-MOSFET，并对其薄膜性能进行了测试，以期应用于ALD高k介质/AlD氮化硅叠加栅介质。AlD氮化硅的电子迁移率最大值约为SiO_2的80%，但热载流子诱导和直接隧穿注入引起的晶体管迁移率退化小于SiO_2。这被认为是由于ALD氮化硅比SiO_2产生的界面和体陷阱更小。因此，ALD氮化硅栅介质有可能用于65 nm工艺节点的产生(EOT=1.0 nm)。

Till 2001 fiscal year, atomic-layer deposition (ALD) of ZiO_2 for the next generation gate dielectrics has been studied using (ZTB:Zr(t-OC_4H_9)_4) and H_2O. Also, an ultrathin Si nitride layer as a barrier layer for the interfacial layer was deposited on a Si substrate by ALD. Then, ALD ZiO_2 was deposited on the ALD Si nitride, forming the stack gate structure. The ALD Si-nitride layer successfully suppressed the formation of an SiO_2 interfacial layer. In 2003 fiscal year, more detail study of the growth was carried out to examine the film quality and ALD mechanism. Leak current characteristics were examined for capacitors and the current was found to be due to direct tunneling both for ALDZrO_2/ALD Si-nitride stack gate dielectrics and ALDZrO_2 gate dielectrics. Also, to suppress interface reaction between poly-Si gate and gate dielectrics, the possibility of Si nitride formation using ALD on ZrO_2 was examined. On the other hand, the possibility of HfO_2 was examined using the alternate exposure of Hf(HFAcAc)_4 and H_2O because HfO_2 is the most promising candidate for the future high-k gate dielectrics. However, films with good quality could not be obtained. n-MOSFETs with ALD Si-nitride gate dielectrics (EOT=2.3 nm) were fabricated to evaluate the thin film property for the application to the ALD high-k dielectric/ALD Si-nitride stack gate dielectrics. The maximum value of electron mobility for the ALD Si nitride is about 80% compared with that for SiO_2. However, hot-carrier induced and direct tunneling injection induced mobility degradation in transistors is smaller for the ALD Si nitride than for SiO_2. This is considered to be due to the smaller interface and bulk trap generation for the ALD Si nitride than for SiO_2. Therefore, the ALD Si-nitride gate dielectrics has a possibility to be used for 65 nm technology node generation (EOT= 1.0 nm).