Design Methodology for Advanced VLSI Systems with Heterogeneous Timing

在这项工作中，我们提出了一种基于可扩展延迟不敏感(SDI)模型的局部定时VLSI系统的设计方法。在SDI模型中，虽然假设门和线的延迟是无界的，但得到的是门和线之间的相对延迟信息。因此，利用这样的信息，可以设计出面积和性能最优的VLSI系统。此外，我们还开发了Ainos CAD系统和设计库，为提出的设计方法提供了方便。在Ainos中，接受Verilog RTL描述作为输入，并综合相应的异步系统。在综合过程中，插入实现异步通信的握手信号对，产生控制握手信号的电路，实现握手信号的时序验证。由于Ainos接受常用同步系统设计中使用的相同描述，只要熟悉Verilog描述，就可以很容易地设计局部定时系统，结合Ainos的开发，提出了几种局部定时VLSI系统的逻辑综合方法。首先，为了解决线延迟问题，我们提出了一种电路接口对线延迟不敏感的设计方法。结果表明，该电路可以在任意输入线延时下正常工作。其次，为了优化异步控制电路，我们扩展了一种称为转换法的布尔优化方法，将其应用于异步控制电路。最后，提出了一种采用可变延迟运算单元控制数据通路电路的控制电路设计方法。

In this work, we proposed a design method for locally timed VLSI systems in terms of a scalable delay insensitive (SDI) model. In the SDI model, although unbounded gate and wire delays are assumed, the relative delay information among gates and wires is obtained. Therefore, by using such an information, area and performance optimum VLSI systems can be designed. In addition, we developed the CAD system named AINOS and the design library to facilitate out proposed design method. In AINOS, a Verilog RTL description is accepted as the input and corresponding asynchronous system is synthesized. During the synthesis, pairs of handshake signals to realize asynchronous communication are inserted, circuits to control handshake signals are generated, and the timing verification for handshake signals is realized. Since AINOS accepts the same description used in commonly used synchronous system designs, one can design locally timed systems easily if he is familiar with the Verilog description.Together with AINOS development, we proposed several methods for the logic synthesis of locally timed VLSI systems. At first, to solve the wire delay problem, we proposed a design method so that the interface of circuits is insensitive to wire delays. As a result, the circuit can correctly operate under arbitrary wire delay for input wires. Next, to optimize asynchronous control circuits, we extended a boolean optimization method named transduction method to apply it for asynchronous control circuits. At last, we proposed a design method of control circuits to control data-path circuits with variable delay arithmetic units.