Self assembly of quantum dot and application to electron device using bio-nano process
Self assembly of quantum dot and application to electron device using bio-nano process
批准号:
15360191
负责人:
FUYUKI Takashi
金额:
$9.66万
依托单位国家:
日本
项目类别:
Grant-in-Aid for Scientific Research (B)
财政年份:
2003
资助国家:
日本
项目状态:
已结题
起止时间:
2003 至 2004
中文摘要
随着量子器件的广泛应用,人们对硅纳米晶点进行了研究。硅纳米晶点的特点是与传统的硅工艺兼容,制备工艺简单。作为硅纳米晶点最有前景的应用,浮栅存储器在多项工作中被提出。据悉,硅点适用于存储器件。纳米晶点存储器的特点是对隧道氧化层击穿具有极高的可靠性。在这项工作中,我们提出了一种新的侧壁式等离子体增强化学气相沉积(PECVD)沉积技术。这种方法在低温下(430℃)提供了硅纳米晶体的形貌,隧道氧化层的损伤比平行板式化学气相沉积的损伤要小。我们首次成功地研制出了PECVD法制备的硅纳米晶点。我们采用化学气相沉积(CVD)技术,在低温下制作了硅纳米晶点浮栅存储器。为了分析电子行为,我们采用了厚度为3 nm的薄隧道氧化物。我们成功地证实了n沟道金属氧化物半导体场效应晶体管(MOSFET)在点上的充放电效应,并提出了以铁蛋白为核心的浮栅结构。最初,铁芯是三氧化二铁,因此,有必要还原铁芯。我们研究了通过在非晶硅中嵌入磁芯将磁芯还原为导电的方法。XPS测试结果表明,磁芯成功地由Fe2O3转变为Fe2+,为未来新型存储器件的制备提供了新的技术途径。
英文摘要
Si nano-crystal dot is investigated for the wide usage of quantum device. The feature of the Si nano-crystal dot is the compatibility with the conventional Si process and their simple fabrication techniques. As the most promising application of the Si nano-crystal dot, floating gate memory is proposed in several works. It is reported that the Si dot is applicable to the memory devices. The feature of the nano-crystal dot memory is their extreme high reliability to the tunnel oxide breakdown. Even if the oxide is broken down locally, this does not lead to the failure of whole device performance.In this work, we propose a new deposition technique using side-wall typed plasma-enhanced CVD(PECVD). This method provides Si nano-crystal morphology at low temperature (430℃) and the damage of tunnel oxide was lower than parallel plate typed CVD. We have successfully developed the Si nano-crystal dot fabricated by PECVD for the first time. We have fabricated a floating gate memory using Si nano-crystal dot employing the CVD technique at low temperature. In order to analyze the electron behavior, we employed the thin tunnel oxide with a thickness of 3 nm. We have successfully confirmed the charging and discharging effect in the dot of n-channel metal-oxide-semiconductor-field effect transistor (MOSFET).Furthermore, we proposed to use the core of ferritin protein as floating gate. Initially, the core is ferric oxide, therefore, reduction of the core is necessary. We investigate the reduction method of the core to conductive by embedding the core in the amorphous silicon. XPS signal revealed that the core was successfully changed from Fe2O3 to Fe.This study provides the new technique for fabricating new memory device in the future.
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Siナノドットメモリにおけるート酸化膜厚依存性
硅纳米点存储器中氧化膜厚度的依赖性
DOI:
--
发表时间:
2005
期刊:
第50回応用物理学関係連合講演会 1a-P6-19
影响因子:
--
作者:
[P.Punchaipetch, 市川和典, 矢野裕司, 畑山智亮, 浦岡行治, 冬木隆, 高橋英治, 林司]
通讯作者:
林司
Si-Wall電極型PECVDによるSiナノドットにおける充放電特性評価
使用Si-Wall电极型PECVD评估Si纳米点的充放电特性
DOI:
--
发表时间:
2004
期刊:
第65回応用物理学関係連合講演会 1a-L-lO
影响因子:
--
作者:
[市川和典, P.Punchaipetch, 矢野裕司, 畑山智亮, 浦岡行治, 冬木隆, 高橋英治, 林司]
通讯作者:
林司
Si nano-crystal dot memory fabricated by Side-wall Typed PECVD
侧壁式PECVD制备硅纳米晶点存储器
DOI:
--
发表时间:
2004
期刊:
Technical Report of IEICE SDM2004-206
影响因子:
--
作者:
[Kazunori Ichikawa, Masato Mukai, P.Punchaipetch, Hiroshi Yano, Tomoaki Hatayama, Yukiharu Uraoka, Takashi Fuyuki, Eiji Takahashi, Tsukasa Hayashi, Kiyoshi Ogata]
通讯作者:
Kiyoshi Ogata
積層型Siナノドットフローティングゲートメモリにおける充放電特性評価
堆叠式硅纳米点浮栅存储器充放电特性评估
DOI:
--
发表时间:
2005
期刊:
第50回応用物理学関係連合講演会 1a-P6-19
影响因子:
--
作者:
[市川和典, P.Punchaipetch, 矢野裕司, 畑山智亮, 浦岡行治, 冬木隆, 高橋英治, 林司]
通讯作者:
林司
Electron Injection into Si nano dot fabricated by Side-wall type plasma enhanced chemical vapor deposition
电子注入侧壁型等离子体增强化学气相沉积硅纳米点
DOI:
--
发表时间:
2005
期刊:
IEEE/International Meeting for Future Electron Devices, Kansai P-D7
影响因子:
--
作者:
[Kazunori Ichikawa, Masato Mukai, P.Punchaipetch, Hiroshi Yano, Tomoaki Hatayama, Yukiharu Uraoka, Takashi Fuyuki, Eiji Takahashi, Tsukasa Hayashi, Kiyoshi Ogata]
通讯作者:
Kiyoshi Ogata
共 13 条
Random Tunneling Conduction in 2 Dimensional Bio-nano Dot Arrays and Application to Stochastic Resonant Tunneling Devices
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批准号:18360173
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项目类别:Grant-in-Aid for Scientific Research (B)
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资助金额:$10.4万
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财政年份:2006
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负责人:FUYUKI Takashi
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依托单位:
海外基金