Artificial resilience using learning-based test and debug for future intelligent systems

在今天和未来的复杂计算系统中，由几个具有混合临界程度的硬件和软件组件组成，具有不断变化的需求（例如，性能和功能）和资源（例如，能源），加上由于纳米级制造技术而产生的新的和复杂的故障机制，此外，还受到复杂的设计错误和恶意攻击。在设计中使用硬编码冗余的暴力破解方案和固定的运行时恢复策略已不再足够。不断增加的设计复杂性，以及软件运行时行为和设备级参数之间复杂的相互作用，这些都不是很完全理解或准确建模，导致Heisenbugs逃避硅前验证。容错、制造测试和硅后调试这三个相互依赖的领域，尽管有着共同的复杂且难以建模的弹性根源，但在过去一直存在分歧，每个领域都试图用不相关的设计基础设施和解决方案集来解决这些问题。这在一定程度上是因为它们是独立的领域，属于不同的学术研究团体和行业部门。它们每个都针对特定类型的故障和故障，基于非常严格的空间和时间冗余，硬编码到系统的设计中，这在面积、能量和性能方面产生了过高的复杂性和成本。然而，由于从硬件设计、制造到现场操作的问题越来越复杂和不确定性，传统的基于电路和系统二进制逻辑状态分析的确定性解决方案变得越来越低效。此外，添加不同的设计基础设施和解决方案以单独解决这些问题的复杂性不再是可扩展的。该建议的主要目的是通过一组跨越计算系统的不同设计、测试和操作生命周期的整体方法来追求人工弹性，这样它们就可以在组件故障、环境干扰和设计错误的情况下继续提供所需的功能。我们提出的基于传感器丰富架构和基于学习的传感器数据分析的人工弹性范式是本项目的主要新颖之处。我们还将研究，作为可行性研究和概念验证，如何将这一概念定制，以应对制造测试、后硅调试和可靠系统设计等不同领域的具体挑战和问题。

In complex computing systems of today and future, consisting of several hardware and software components with mixed degrees of criticality, with changing requirements (e.g., performance and functionalities) and resources (e.g., energy), coupled with new and complex failure mechanisms due to nanometer scale fabrication technology, and in addition, subject to complex design bugs and malicious attacks, brute force schemes with hardcoded redundancies in the design and fixed runtime recovery policies are no longer sufficient. The increasing design complexity together with complex interactions of runtime behavior of software and device-level parameters, which are not very fully understood nor accurately modeled, cause Heisenbugs to escape pre-silicon validation. The interdependent fields of fault tolerance, manufacturing test, and post-silicon debug, although sharing common sets of complex and hard-to-model resiliency root causes, have been diverging in the past, each trying to address these problems with disjoint sets of design infrastructures and solution. This is partly because these are separate fields, in different academic research communities and industry divisions. They each target particular classes of failures and malfunctions, based on very rigid spatial and temporal redundancies, hardcoded into the design of the system, which incur exorbitant amount of complexity and costs in terms of area, energy, and performance. However, due to the increasing complexity and non-determinism of the problems, spanning from hardware design, manufacturing and in-field operation, traditional deterministic solutions mostly based on analysis of binary logic states of the circuit and system, becomes more and more inefficient. Also, the complexity of adding different design infrastructure and solutions, to target these issues in isolation, is no longer scalable. The main purpose of this proposal is the pursuit of artificial resilience, through a set of holistic approaches spanning over different design, test and operation lifecycles of computing systems, such that they can continue to provide required functionality despite malfunctioning components, environmental disturbances, and design bugs. Our proposed artificial resilience paradigm, based on a sensor rich architecture and learning-based analysis of sensor data, is the main novelty of this project. We will also investigate, as a feasibility study and proof-of-concept, how this concept can be tailored to deal with specific challenges and problems in different fields of manufacturing test, post-silicon-debug, and reliable system design.