Research on Low-Power Design of Microprocessor Systems.

利用LSI的特点，我们提出了新的低功耗微处理器系统设计技术。研究内容包括处理器和存储器的低功耗体系结构、电源电压的最优控制策略以最小化功耗、以及低功耗设计的硬件/软件协同设计技术。1)开发了具有可变电压处理器架构的低功耗系统：在该架构中，我们提供了几个电源电压电平和对应于每个电压电平的时钟频率。程序员可以根据程序所需的负载选择最佳的电压电平。我们证明了一个选择最佳电压的基本定理，并用一条电压控制指令实现了一个原型处理器。对于实际程序，功耗降低了70%以上。2)可变数据路径宽度低功耗处理器的开发：我们提出了一种新的处理器体系结构，可以通过程序控制有效数据路径宽度。该体系结构可以很容易地与基于软核处理器的软硬件协同设计技术相结合。3)一种减少总线转换的编译器技术和一种高速缓冲存储器的低功耗设计技术：我们提出了一种控制指令和数据在总线上的编码和传输顺序的编译器技术。4)逻辑-DRAM混合LSI的低功耗体系结构：针对逻辑-DRAM混合LSI的存储层次结构，我们提出了一种减少DRAM刷新次数以最小化存储系统功耗的技术。5)低功耗电路的逻辑综合方法的发展：我们提出了一种新的逻辑综合算法和转换法相结合的方法来生成最小功耗的组合电路。

We proposed novel design techniques for low-power consumption microprocessor systems utilizing characteristics of LSIs. The research covers low-power architectures of processors and memories, an optimum control strategy of supply voltage for minimizing power consumption, and hardware/software codesign techniques for low-power design. The following results have been obtained.1) Development of low-power systems with a variable voltage processor architecture : In this architecture, we provide several supply voltage levels and clock frequency corresponding to each voltage level. Programmers can select the optimum voltage levels according to the required load of programs. We proved a basic theorem for the selection of the optimum voltage and implemented a prototype processor with a voltage control instruction. More than 70% power reduction is achieved for practical programs.2) Development of a low-power processor with variable data-path width : We proposed a new processor architecture in which active data-path width can be controlled from programs. This architecture can be easily combined with the hardware/software codesign technique based on Soft-core processor.3) A compiler technique for reducing bus transitions and a low-power design technique of cache memories : We proposed a compiler technique which controls coding and order of transfer of instructions and data on buses. We also developed a power reduction method in which instructions and data read from cache memory are expected.4) A low-power architecture of logic-DRAM mixed LSIs : For the memory hierarchy of logic-DRAM mixed LSI, we have proposed a. technique to reduce the number of refresh of DRAM to minimize the power consumption in the memory system.5) Development of logic synthesis method for low-power circuits : We developed a new logic synthesis algorithm combined with Transduction method to generate the power minimum combinational circuits.