Data-Driven Ultra-Parallel Processing Scheme Based on "Flow-Thru Processing" Concept

本研究是为了在超大规模集成电路（VLSI）芯片上实现超并行处理方案，引入“流通处理”的概念。为了建立高度并行算法的基础，我们采用了质数生成（Eratosthenes筛）等例子，其中目标问题中存在的高度并行性必须在没有任何副作用的情况下执行。我们已经证明，基于“流式处理”概念的弹性管道在利用这种并行性方面是有效的。1）. 其次，实现了同样基于“流式处理”概念的单板数据驱动处理器系统，并作为一个强大的实验系统。利用系统的监控设施，我们已经确认了20个MOPS的目标性能(参考号：3)。对该系统的浮点处理器ALU（参考编号：1139111111）进行了40 MFLOPS的性能评估。4)。评估也证实了每秒50兆次的射击控制功能。5)。受到这些结果的鼓舞，我们制作了一个单片数据驱动处理器的原型，作为评估芯片，其性能达到50 MFLOPS(参考编号：。6)。针对可编程逻辑阵列的现场可编程性，我们也开始了对变结构弹性管道的初步研究，以实现具有更灵活能力的处理器。当这样一个强大的单处理器相互连接时，也可以作为大规模多处理器系统的处理元件，有望实现传统处理器迄今未能实现的性能突破。提出了一种基于催化环的自主分布式并行关联处理器，其中两个弹性管道在相反方向流动的同时又相互作用。目前，我们已经开始对自主分布式联想处理进行评估，预计这将在我们对高度并行处理方法的研究中发挥基础作用，以实现下一代知识处理。少

This research was initiated to realize the ultra parallel processing scheme on a VLSI chip by introducing the "flow-thru processing" concept. In order to establish a basis for highly parallel algorithms, we have undertaken such examples as the prime number generation (Sieve of Eratosthenes) in which high parallelisms existent in the target problem must execute without any side effects. We have shown that the elastic pipeline based upon the "flow-thru processing" concept is effective in exploiting such parallelisms (reference no. 1). Next, a single board data-driven processor system also based upon the "flow-thru processing" concept was realized and has served as a powerful experimental system. Using the system's monitoring facilities, we have confirmed the targeted performance of 20 MOPS (reference no. 3). Performance evaluations of 40 MFLOPS were exhibited for the system's ALU, the floating point processor (reference no. 4). Evaluations also confirmed 50 mega associations per second f … More or the firing control function (reference no. 5). Encouraged from these results, a prototype of the one chip data-driven processor was fabricated as an evaluation chip which yielded performance of 50 MFLOPS (reference no. 6).Focusing upon the field programmability of programmable logic arrays, we have also began preliminary examination on variable structure elastic pipelines in order to realize a processor with more flexible capabilities.When interconnected, such a powerful single processor can also serve as processing elements in large scale multiprocessor system which promises to achieve breakthroughs in performance thus far unsuccessful with conventional processors. An antonomous distributed parallel associative processor coined the catalytic ring has been proposed in which two elastic pipelines flow in opposite directions while at the same time interacting with each other. We have currently began evaluations on autonomous distributed associative processing which is expected to play a fundamental role in our research toward highly parallel processing methodology to realize the next generation of knowledge processing. Less