STUDY ON SCHOTTKY TUNNEL TRANSISTOR

肖特基隧道晶体管将有潜力成为ULSI器件（如DRAM）的突破性器件，因为该器件将克服阻碍更小型化MOSFET的短通道效应，并定位在单电子晶体管之间，预计将成为未来的晶体管和现有最小型化的MOSFET。在1996年，我们研究了以下项目：1。2.通过齐纳二极管的形成保护栅氧化膜。考虑器件制造工艺的肖特基障壁金属和栅极金属的选择；零偏置电压下肖特基隧道电流的实验研究为肖特基隧道电流流动模型。在上述研究中，获得了肖特基隧道晶体管的基本特性，并证实它可以克服伴随通道长度减小而产生的短通道效应。这种肖特基隧道晶体管结构简单，在肖特基隧道二极管的结上覆盖一个很短的MOS栅极。然而，很明显，这种肖特基隧道晶体管的Gm太小，不能用作ULSI的DRAM。因此，在1997年，我们研究了以下几个项目：1。2.转基因为何如此之小的研究。2 .结构有效肖特基高度和隧道长度变化的研究；具有较大Gm的mos栅极肖特基隧道晶体管的新结构及其制备。这种新结构在肖特基金属和衬底的n+表面层之间有一个约3um厚的p+层，该p+层的势垒高度由MOS栅电压和电子穿过该势垒来控制。这种极薄的p+层是由Al扩散和合金通过钴硅化层作为肖特基金属制成的。结果，我们得到了具有预期三极管I-V特性的MOS门-肖特基隧道晶体管。

Schottky tunnel transistor will have a potential to be a break-through device for ULSI devices such as DRAM,because this device will overcomes the short channel effects which has prevented to more miniaturize MOSFETs and is positioned between single-electron transistor expected as a future transistor and existing most miniaturized MOSFET.In 1996 we studied about following items : 1.Protection of the gate oxide film by formation of the Zener diode, 2.Selections of Schottky barrier metal and gate metal taking account of device fabrication process, 3.Experimental studies on Schottky tunnel current near zero bias voltage for the model of the Schottky tunnel current flow. In above studies the fundamental characteristics of the Schottky tunnel transistor was obtained, and it was confirmed to overcome the short channel effects accompanied in the reduction of the channel length as expected. This Schottky tunnel transistor has a simple structure in which a very short MOS gate is overlayd on the junction of the Schottky tunnel diode. However, it has been clear that this Schottky tunnel transistor has too small Gm to use as a DRAM of ULSI.Therefore in 1997 we studied on about following items : 1.Studies on the reason why Gm is so small, 2.Studies on structures to vary the effective Schottky height as well as tunnelling length, 3.New structure of MOS-gate Schottky tunnel transistor with relatively large Gm and its fabrication. this new structure has a p+ layr of about 3 um thick between the Schottky metal and n+ surface layr in the substrate, and barrier height of this P+ layr is countrolled by the MOS gate voltage and electrons tunnel this barrier. This very thin p+ layr was fabrication by Al diffusion and alloy through the cobalt siliside layr as a schottky metal. As a result we have gotten the MOS gate-Schottky tunnel transistor with expected triode I-V characteristics.