Aconstruction of a routing synthesis system for VLSI packages

本研究旨在建构一套实用的BGA封装自动化布线综合系统。在我们的BGA模型中，有两个布线层，小于封装尺寸的单个芯片放置在第一层上，键合指放置在第一层上包围芯片的矩形的周边上，焊球放置在第二层上的网格阵列图案中，连接要求被给出为连接键合指和焊球的两个端子网，并且通过使用层1和层2上的导线以及连接它们的通孔来实现。此外，为了能够在不增加制造成本的情况下提高可靠性的电镀，将称为电镀引线的额外导线添加到每个网。电镀引线将网的导线连接到围绕封装的金属环。在我们的传统系统中，布线图案中，第一层上的导线是单调的，而电镀引线是在第一层上的探索，并通过迭代地修改过孔分配来改进。然而，设计人员并不一定满意所获得的布线图案，因为第二层上的布线不一定完成，并且有时会由于布线区域中的障碍物而导致若干拥塞错误。在这项研究中，我们加强了我们的传统系统，使第二层的可路由性是通过使用路由图生成第二层的路由保证。此外，我们的系统考虑到的障碍，采用新型的过孔分配修改，有效地减少布线拥塞，提高了电镀引线的层分配，有效地利用布线资源在第二层，并处理电源网络的电镀引线。结果，系统性能得到改善，并通过该系统得到的路由模式的评价。我们的系统生成的布线模式相当于设计师在几秒钟到几分钟内获得的模式。

The purpose of this research is to construct a practical automated routing synthesis system for BGA packages. In our BGA model, there are two routing layers, single chip which is smaller than package size is put on layer-one, bonding fingers are placed on the perimeter of a rectangle enclosing the chip on layer-one, solder balls are placed in a grid array pattern on layer-two, the connection requirement is given as two terminal nets that connect a bonding finger and a solder ball, and it is realized by using wires on layer-one and layer-two and vias that connect them. Further, in order to enable electric plating that improves reliability without increasing fabrication cost much, a extra wire, called plating lead, is added to each net. A plating lead connects the wire of a net to the metal ring that surrounds the package. In our conventional systems, routing patterns in which wires on layer-one are monotonic and which plating leads are on layer-one are explored, and improved by modifying via assignment iteratively. However, designers are not necessarily satisfied with the obtained routing patterns since the routing on layer-two is not necessarily completed and the several congestion errors are sometimes caused by obstacles in routing region. In this research, we enhanced our conventional systems so that the routability on layer-two is guaranteed by generating routing on layer-two by using a routing graph. Also, our system takes the obstacles into account, adopts new type of via assignment modifications that effectively reduce the routing congestion, improves the layer assignment of plating leads to utilize routing resources in layer-two efficiently, and handles plating leads of power nets. As the result, the system performance is improved and the evaluation of routing pattern obtained by the system is improved. Our system generates routing patterns equivalent to patterns obtained by designers within several seconds to several minutes.