Gather-Level Parallelism

现代大数据工作负载目前运行在不适合从中提取高性能的处理器上。这些工作负载以不可预测的模式从DRAM主存储器请求数据，因此现有的硬件和软件解决方案在预测所需的高延迟工作方面是无效的。今天的计算机处理器总是在等待数据从内存返回，吞吐量低，执行效率低。未开发的潜力是巨大的。许多大数据工作负载显示出内存级并行的潜在形式，其中复杂的操作序列可以重新排序和重叠，以隐藏大部分延迟，从而实现高吞吐量。虽然计算限制的工作负载得到了特殊向量指令的极大帮助，这些指令同时计算许多操作，但内存限制的大数据工作负载还不能这么说。这个项目试图将计算并行性与内存并行性结合起来。我们将重新设计内存访问方法，并考虑到矢量化。这将使我们能够同时预取或预测许多复杂的计算和内存访问序列的需求。我们相信，有可能使高性能，高效的软件预取机制，作为专用硬件的性能。我们的新机制将利用一个新的概念，称为并行级并行，通过利用和重新设计向量的方法来实现极端的内存级并行，而不会打破银行的可编程计算。为了取得成功，我们将需要在编译器和底层硬件架构中进行新的更改。聚集级并行性将为当今系统中访问内存的方式带来范式转变。在大数据工作负载已经效率低下的时代，这一点尤为紧迫，并且受到消除当今计算机处理器中最近发现的Spectre漏洞所需的安全缓解措施的进一步威胁。由于用于隐藏漏洞的限制，这些会导致内存延迟方面的更大挑战，从而使高性能内存技术变得更加紧迫。在性能和安全性之间做出选择的现状，在通常敏感的大数据上，不能允许继续下去。

Modern big-data workloads are currently run on processors that are ill suited to extracting high performance from them. These workloads request data from DRAM main memory in unpredictable patterns, and so existing hardware and software solutions are ineffective at anticipating the high-latency work that is necessary. Today's computer processors are constantly stalled waiting for data to return from memory, with low throughput and inefficient execution.The untapped potential is significant. Many big-data workloads show potential forms of memory-level parallelism, where complex sequences of operations can be reordered and overlapped to hide much of the latency, and thus achieve high throughput. While compute-bound workloads have been greatly aided by special vector instructions, which calculate many operations simultaneously, the same cannot yet be said for memory-bound big-data workloads. This project seeks to marry compute parallelism with memory parallelism. We will redesign memory access methods with vectorisation in mind. This will allow us to prefetch, or anticipate the demands of, many complex sequences of compute and memory access all at once. We believe it is possible to make high-performance, efficient software mechanisms for prefetching that are as performant as dedicated hardware. Our new mechanisms will exploit a new concept called gather-level parallelism, by utilising and redesigning vector methods to achieve extreme memory-level parallelism without breaking the bank on programmable compute. To succeed, we will require new changes throughout both the compiler and the underlying hardware architecture.Gather-level parallelism stands to bring about a paradigm shift in how memory is accessed in today's systems. This is particularly pressing in an era where big-data workloads are already inefficient, and threatened further by the security mitigations necessary to eliminate the recently discovered Spectre vulnerabilities in today's computer processors. These cause even greater challenges in memory latency due to the restrictions used to hide vulnerabilities, thus making high-performance memory techniques even more pressing. The status quo, a choice between performance and security, on big data that is often sensitive, cannot be allowed to continue.