Demonstrating SiC CMOS with a self-aligned gate

碳化硅是一种宽禁带半导体，具有电力电子的特殊性能，在最近的SEP展示会(约克)的主旨中进行了介绍。商用碳化硅MOSFET的载流能力差、栅氧化层质量差以及相应的低工作温度(175℃)是其局限性。在UPE的资助下(EP/R00448X/1)，我们通过纳米尺度的栅极重新设计使nMOSFET(DOI：10.1109/TED.2019.2901310)的性能提高了10倍，这可能会提高可靠性和工作温度。确认pMOSFET和开发自对准栅极将是一项具有国际意义的成就，将提高智能碳化硅功率电子产品(与硅相比，占地面积更小，工作温度更高)。

Silicon Carbide is a wide band-gap semiconductor with exceptional properties for power electronics, covered in the keynote at the recent SEP showcase (York). Commercial SiC MOSFETs are limited by poor current carrying capability, gate oxide quality and corresponding low operating temperature (175C). With UPE funding (EP/R00448X/1) we obtained 10x improvement for nMOSFETs (DOI:10.1109/TED.2019.2901310) by nm scale re-engineering the gate that will likely improve reliability and operation temperature. Confirming pMOSFET and developing a self-aligned gate will be an achievement of international significants, enhancing smart SiC power electronics (smaller footprint and higher operational temperature compared with Si).