Low-power logic design using structured logic blocks

半导体行业每隔两三年就继续缩小晶体管的尺寸。这允许更多的晶体管被放置在同一芯片上。在这一点上，晶体管被认为几乎是免费的。然而，集成电路的制造方式变得越来越复杂，并且由于精细的几何形状而出现了新的问题。此外，芯片本身需要更多的时间来设计，成本更高，难以测试，消耗更多的功率。需要新的设计方法和软件工具来解决所有这些问题。本研究探讨一种替代方法来设计逻辑电路，使其易于实施，测试和制造。由于晶体管很便宜，现在是时候重新检查和改进结构化逻辑阵列，然后评估它们作为主流逻辑设计风格的适用性。结构化逻辑阵列的优点是它具有更容易制造的规则布局，并且它还具有使设计自动化相对简单的功能。它还可以使用内置的自测试和自修复技术进行自动测试和校正。然而，这些阵列在时序、功率和面积方面具有开销。 本研究将尝试改善逻辑阵列的这三个方面，并确定它们是否可以与标准设计技术竞争。总体目标是证明结构化逻辑阵列是未来芯片设计的最可行方法，因为晶体管的尺寸不断缩小。

The semiconductor industry continues to shrink the size of the transistor every two or three years. This allows more transistors to be placed on the same chip. At this point, transistors are considered to be almost free. However, the way that integrated circuits are fabricated is getting more complex and new problems have surfaced due to the fine geometries. Furthermore, the chips themselves are taking more time to design, incur higher costs, are difficult to test and consume more power. New design methods and software tools are needed to address all these issues. This research investigates an alternative method to designing logic circuits that lends itself to ease of implementation, test and fabrication. Since transistors are cheap, it is time to re-examine and improve structured logic arrays and then assess their suitability as a mainstream logic design style. The advantage of a structured logic array is that it has a regular layout that is easier to fabricate and it also has features that make design automation relatively straight-forward. It is also amenable to automatic testing and correction using built-in self-test and self-repair techniques. However, these arrays have overhead in terms of timing, power and area.  This research will attempt to improve these three aspects of logic arrays and determine if they can compete with the standard design techniques. The overall goal is to demonstrate that structured logic arrays are the most viable approach for future chip designs, as the transistors continue to shrink in size.