A unified congestion driven power aware methodology for VLSI physical design automation

芯片和板上集成电路的布局(物理设计)是VLSI电路设计中众多相互关联的复杂任务之一。设计自动化领域的大部分研究一直致力于开发支持电路布局的高效和易于使用的系统。今天的嵌入式系统包含微处理器、存储器和专用集成电路(ASIC)形式的不同组件的各种组合。如果没有先进和合适的CAD工具，包括物理设计自动化，所有这些都是不可能实现的。VLSI电路中的互连延迟已经成为电路性能的关键决定因素。在高性能处理器和片上系统设计轨迹的早期就了解互连对速度和功耗的影响似乎变得越来越重要。因此，电路布局开始在当今的芯片设计中发挥更重要的作用。

The layout of integrated circuits on chips and boards (physical design) is one of many interrelated complex tasks in VLSI circuit design. A major portion of the research in the area of design automation has been devoted to the development of efficient and easy-to-use systems that support circuit layout. Today's embedded systems contain various combinations of different components in the form of microprocessors, memories and application specific integrated circuits (ASICS). All this cannot be achieved without advanced and suitable CAD tools including physical design automation. The interconnect delay in VLSI circuits has become a critical determiner of circuit performance. It seems to become more and more important to know the impact of interconnection on speed and power consumption early in the design trajectory of high-performance processors and Systems-on-Chip. As a result, circuit layout is starting to play a more important role in today's chip designs.