Dynamic delay fault testing of high-performance digital circuit in deep submicron technology

在过去的30年里，积极的技术缩放一直是数字CMOS电路设计的支柱。它导致了千兆赫集成电路（IC）的设计和前所未有的集成度。现代集成电路的时钟频率超过3千兆赫，其芯片包含近3亿个晶体管。数字集成电路的性能遵循摩尔定律，每年提高30%。然而，ATE的性能每年仅提高12%。ATE边缘放置精度与被测电路（CUT）性能之间的差异将使未来深亚微米技术（DSM）的高速逻辑测试变得越来越困难。

Aggressive technology scaling has been the mainstay of digital CMOS circuit design for the past 30 years. It has resulted in the design of multi-gigahertz integrated circuit (IC) and unprecedented levels of integration. Modern integrated circuits operate at clock frequencies of more than 3 GHz, and their dies contain close to 300 million transistors. Digital IC performance has followed Moore's law, improving annually by 30%. However, ATE performance has improved by only 12% annually. The discrepancy between ATE edge placement accuracy and circuit under test (CUT) performance1 will make at-speed logic testing increasingly difficult for future deep-submicron technologies (DSM).