A configurable profiling core for multicore processors

多年来，处理器设计人员能够充分利用摩尔定律，该定律指出，集成在单个芯片上的组件密度随时间呈指数级增长。 随着芯片密度的增加，芯片时钟速率以前一直遵循大约每18个月翻一番的趋势。 然而，由于处理器的功率需求不断增加，这种时钟频率缩放不再可能。 相反，处理器制造商已经转向设计多核处理器系统，增加可能的并行性，而不是利用不断增加的芯片密度，同时时钟速率保持相对恒定。 据预测，多核系统中的处理器数量最终将扩展到10个和100个。 这对操作系统（OS）来说是一个巨大的挑战，它必须确定如何在这些复杂的系统上有效地调度任务。 操作系统将如何确定如何调度线程以最小化缓存争用，以及哪些处理器满足异构系统上每个任务的执行要求？ 当前，许多硬件计数器被包括作为处理器架构的一部分，其使得能够在运行时对应用程序进行有限的剖析。 然而，这些不提供足够的灵活性或信息来有效地指导OS进行任务分配。 虽然现有计数器报告问题的症状（即，该高速缓存未命中率有多大），但是它们不能提供关于问题发生的原因以及如何修复的洞察。所提出的分析核心将为操作系统和应用程序提供有关运行时性能瓶颈的详细信息，并使它们能够通过调度或动态编译来解决这些瓶颈。因此，应用程序软件将能够更好地利用多核硬件平台的固有特性，无论是同构还是异构。此外，分析功能将被隔离在一个单独的核心上，这将有助于通过IP重用将丰富的分析功能纳入新的处理器。当与商用多核处理器结合使用时，该研究项目有可能显著改善客户的体验和生产力。

For years, processor designers were able to fully leverage Moore's Law, which states that the density of components integrated on a single chip grows exponentially over time. In conjunction with increasing chip density, chip clock rates have previously been following a trend of doubling approximately every 18 months. However, due to the increasing power requirements of processors, this clock frequency scaling is no longer possible. Instead, processor manufacturers have moved to designing multi-core processor systems, increasing possible parallelism instead to leverage the increasing chip density while clock rates remain relatively constant. It is predicted that the number of processors in multi-core systems will eventually scale to the 10s and 100s. This becomes a significant challenge for the Operating System (OS), which has to determine how to schedule tasks effectively on these complex systems. How will the OS determine how to schedule threads so as to minimize cache contention and which processor(s) meet each task's execution requirements on heterogeneous systems? Currently a number of hardware counters are included as part of a processor's architecture that enable limited profiling of applications at run time. However, these do not provide sufficient flexibility or information to effectively guide the OS in task assignment. While existing counters report the symptoms of a problem (i.e., how large the cache miss rate is), they do not provide insight into why the problem has occurred and how it could be fixed. The proposed profiling core will provide both operating systems and applications with detailed information about run time performance bottlenecks and will enable them to address these bottlenecks via scheduling or dynamic compilation. As a result, application software will be able to better leverage the intrinsic nature of the multi-core hardware platform, be it homogeneous or heterogeneous. Furthermore, the profiling functionality will be isolated on a separate core, and this will facilitate inclusion of rich profiling functionality into new processors via IP reuse. This research project has the potential to significantly improve a customer's experience and productivity when used in conjunction with commercial multi-core processors.