Utilizing Serial Communication to Improve the Area Efficiency of FPGAs for Implementing Multi-Bit Processing Circuits
Utilizing Serial Communication to Improve the Area Efficiency of FPGAs for Implementing Multi-Bit Processing Circuits
批准号:
327691-2012
负责人:
Ye, Andy
金额:
$1.31万
依托单位:
依托单位国家:
加拿大
项目类别:
Discovery Grants Program - Individual
财政年份:
2014
资助国家:
加拿大
项目状态:
已结题
起止时间:
2014-01-01 至 2015-12-31
中文摘要
本研究的目标是通过有效利用片上串行通信来提高现场可编程门阵列(FPGA)路由资源的区域效率。串行通信已成为提高片间通信面积效率的有效方法。对于fpga来说,使用大量高度灵活的可编程导线将一组高度可编程的逻辑连接在一起,串行通信也可能是提高片内通信面积效率的有效方法。
英文摘要
The goal of this research is to improve the area efficiency of Field-Programmable Gate Array (FPGA) routing resources through the effective use of on-chip serial communication. Serial communication has been an effective method for increasing the area efficiency of inter-chip communications. For FPGAs, where a large number of highly flexible programmable wires are used to connect a set of highly programmable logic together, serial communication potentially can also be an effective method for improving the area efficiency of intra-chip communications.
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