Fabrication and process modeling of silicon based material structures for nanoscale microelectronics and photonics

这项拨款是为了支持一个综合研究计划，在过程建模的硅基材料和工艺与应用纳米电子学和集成光电子学。今后五年将开展两方面的研究： 1. 缺陷和扩散：我们已经发表了关于模拟Si-Ge相互扩散的工作（Hasanuzzaman和Haddara，2008; Hasanuzzaman等人，2009）和对来自硅-氮化硅界面的空位注入进行建模（Hasanuzzaman和Haddara，2008）。我们已经开发出的模型，在裸硅和硅衬底应变SiGe薄膜在不同的环境条件下（进行中）的空隙的生长。我们将这些数据与在相同处理的样品中掺杂剂的扩散行为的测量相结合，以能够获得Si和SiGe中缺陷行为的完整图像。了解Si和SiGe结构中缺陷和扩散行为的全貌对于纳米级微电子器件的工艺建模至关重要，包括缩放MOSFET，高速HBT和新器件结构。 2. 纳米线制造和建模：我们已经报道了我们关于三元纳米线的工作（Fakhr等人，2010），并且已经开发了一种综合的定量模型，该模型解释了线形态、径向和轴向组成以及堆垛层错密度对诸如生长速率、III/V通量比和压力的工艺参数的依赖性（Fakhr等人，进行中）。我们希望将实验和建模扩展到Si/SiGe/SiGeC纳米线。我们将优化这些导线的制造工艺，模拟它们的生长和成分，并研究未掺杂和掺杂导线的电学特性。

This grant is to support an integrated research program in process modeling for silicon-based materials and processes with applications in nanoelectronics and integrated optoelectronics. Two lines of research will be developed over the next five years: 1. Defects and diffusion: We have published work on modeling Si-Ge interdiffusion (Hasanuzzaman and Haddara, 2008; Hasanuzzaman et al., 2009) and on modeling vacancy injection from the silicon-silicon nitride interface (Hasanuzzaman and Haddara, 2008). We have developed models for the growth of voids in bare silicon and in silicon substrates with strained SiGe thin films under different ambient conditions (in progress). We have coupled these data with measurement of diffusion behavior of dopants in identically processed samples to be able to obtain a complete picture of the defect behavior in Si and SiGe. Understanding the full picture of defect and diffusion behavior in Si and SiGe structures is critical for process modeling for microelectronic devices in the nanoscale, including scaled MOSFETs, high speed HBTs, and new device structures. 2. Nanowire fabrication and modeling: We have reported on our work with ternary nanowires (Fakhr et al., 2010) and have developed a comprehensive quantitative model that explains the dependence of wire morphology, radial and axial composition, and stacking fault density on process parameters such as growth rate, III/V flux ratio, and pressure (Fakhr et al., in process). We wish to extend both experiment and modeling to Si/SiGe/SiGeC nanowires. We will optimize the fabrication process for these wires, model their growth and composition, and study the electrical properties of undoped and doped wires.