Development of low-voltage and low-power mixed-signal ICs using nano-scale multiple gate field-effect transistors

低功耗和高性价比的互补金属氧化物半导体(CMOS)器件迫使模拟设计者利用数字CMOS技术开发集成电路(IC)。传统的纳米平面CMOS器件存在漏极感生势垒降低、阈值电压滚降导致漏电流大、本征增益低、输出阻抗低、动态范围小、器件匹配性差等不利的短沟效应。这些非理想性最终会降低CMOS器件的性能，并对IC的性能构成严重威胁。 鳍形场效应管(FinFET)等多栅场效应晶体管是亚32 nm工艺中最有希望取代平面CMOS场效应晶体管的器件。事实上，FinFET技术提供了一些有趣的功能，如严格的沟道控制以缓解短沟道效应，以及更陡峭的亚阈值斜率。 尽管多门技术具有优势，但新的设计挑战尤其出现在模拟、混合信号和射频(RF)电路中。与平面CMOS晶体管相比，FinFET存在更大的寄生问题。窄的鳍片宽度增加了源极和漏极的电阻，导致FinFET的高频和噪声性能下降。此外，栅极和源极/漏极之间的空白区导致晶体管的边缘电容大幅增加，从而降低了射频应用的速度。FinFET器件还表现出在设计模拟和混合信号电路时必须考虑的新的不良影响，即自加热和滞后效应。此外，FinFET器件的准确物理特性对模拟设计者来说是一个巨大的挑战，新的优化布局技术也是充分受益于这一先进技术的必要条件。 因此，为了享受多栅场效应晶体管的优点，本提案的目标是开发使用FinFET的高性能模拟、射频和混合信号电路的新设计方法。

The low-power and cost-effective Complementary Metal-Oxide-Semiconductor (CMOS) devices have forced the analog designers to develop integrated circuits (ICs) using digital CMOS technologies. Conventional nano-scale planar CMOS devices suffer from undesirable short-channel effects, such as high drain induced barrier lowering, substantial leakage currents due to threshold voltage roll-off, lower intrinsic gain, lower output impedance, lower dynamic range and poorer device matching. These non-idealities eventually degrade the performance of CMOS devices and pose a serious threat to ICs' performance. The Multiple gate field-effect transistors, such as Fin-shaped Field Effect Transistors (FinFETs), are emerging as the most promising replacement for planar CMOS in sub-32nm technologies. In fact, FinFET technology offers interesting features such as tight channel control to mitigate short channel effects, and steeper sub-threshold slope. Despite the advantages of multi-gate technologies, new design challenges arise particularly for analog, mixed-signal and radio frequency (RF) circuits. FinFETs suffer from larger parasitic compared to planar CMOS transistors. The narrow fin width increases the source and drain resistances and that result in degrading the high frequency and noise performance of FinFETs. Also the empty region between the gate and the source/drain causes a large increase in the fringe capacitors of the transistor and consequently reduces the speed of RF applications. FinFET devices also show new undesirable effects that have to be taking into consideration while designing analog and mixed-signal circuits; namely self-heating and hysteresis effect. Moreover, accurate physical characterization of FinFET devices represents a tremendous challenge for analog designer and new optimized layout techniques are also necessary to fully benefit from this advanced technology. As a result to enjoy the merit of multi-gate field-effect transistors, the objective of this proposal is to develop novel design methodologies for high performance analog, RF and mixed signal circuits using FinFETs.