Heterogeneous integration of high-density analog crossbar for advanced data processing

信息和通信技术（ICT）目前正在经历重大变革，这将改变我们与电子产品的互动。预计计算系统将出现用于大型、异构和非结构化数据处理的可行解决方案。由于传统系统根本不适合这类问题，因此设想了替代解决方案，并要求在计算范式，架构和技术方面进行彻底转变。为此，生物启发的计算模型出现作为一个有前途的解决方案，传统的计算，因为这些系统可以管理多感官输入非常大的带宽在真实的时间和低能耗。沿着这些路线，人工神经网络近年来重新受到关注，在视觉识别任务和游戏中表现优于人类。然而，这样的系统将极大地受益于沿着计算节点（神经元）的密集、并行和分布式存储器（突触）。在这个项目中，我们建议为机器学习硬件的未来发展建立一个高效和通用的系统，更准确地说，我们提出了一个可扩展的，灵活的和创新的策略，用于实现突触权重和相关的乘法和累积操作（MAC），这是高效ML硬件最苛刻的资源之一。我们将利用CMOS性能和新兴存储器件（即突触）的特定功能之间的理想平衡。HIDATA提出了两个层次的集成：（i）我们将使用先进的系统级封装方法，以优化CMOS芯片上存储器件的异构集成。在这里，我们将设计和制造通过倒装芯片技术互连的存储器芯片，这将确保动态信号管理和路由，同时最大限度地减少存储器设备的可变性和保持CMOS设计的灵活性。(ii)我们将以系统级芯片的策略，透过多重被动式纵横式互连来实现一个大规模平行且密集的记忆体阵列。无源交叉开关之间的有源放大将实现超高存储器密度，同时保持对存储器设备的最佳控制。

Information and Communication Technology (ICT) is currently experiencing significant mutations that will modify our interactions with electronics. Computing systems are expected to emerge with viable solutions for large, heterogeneous and unstructured data processing. Since conventional systems are fundamentally not adapted to this class of problem, alternative solutions are envisioned and demand a complete shift in the computing paradigm, architecture and technology. To this end, the bio-inspired computing model appears as a promising solution to conventional computing since these systems can manage multi-sensory inputs with very large bandwidth in real time and with low energy consumption. Along these lines, artificial neural networks have experienced renewed interest in recent years, outperforming humans in visual recognition tasks and gaming. Nevertheless, such systems would benefit immensely from a dense, parallel and distributed memory (synapses) along the computing nodes (neurons). We propose in this project to build an efficient and versatile system for the future development of machine learning hardware, and more precisely, we propose a scalable, flexible and innovative strategy for the implementation of the synaptic weight and the associated Multiply and ACcumulate operation (MAC), one of the most demanding resource for efficient ML hardware. We will capitalize on an ideal balance between CMOS performance and specific features available with emerging memory devices (i.e. synapses). HIDATA proposes two levels of integration: (i) we will use an advanced system-in-package approach in order to optimize heterogeneous integration of memory devices on CMOS chips. Here, we will design and fabricate memory chips interconnected via flip-chip technology on an active interposer which will ensure dynamic signal management and routing while minimizing memory device variability and preserving CMOS design flexibility. (ii) We will implement a massively parallel and dense memory array via multiple passive crossbar interconnection in a system-on-chip strategy. Active amplification between passive crossbars will enable ultra-high memory density while preserving optimal control of the memory devices.